clk: at91: Add ACR in all PLL setting.

Add ACR in all PLL setting. Add correct ACR value for each PLL used in
different SoCs.

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 580c9964ff4dc5b151d967f01a87b2cdc9374fab..f38868d16655fc489dc3e8984e3b38ab07dfb356 100644 (file)
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -42,6 +42,7 @@ struct clk_pll_characteristics {
        u16 *icpll;
        u8 *out;
        u8 upll : 1;
+       u32 acr;
 };
 
 struct clk_pll_layout {

diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index e04266a2be22b541ab2a935ff4a532a9900df0e1..2251e2846fa787ab4494127b1892a0695ad657f8 100644 (file)
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -123,6 +123,7 @@ static const struct clk_pll_characteristics apll_characteristics = {
        .num_output = ARRAY_SIZE(plla_outputs),
        .output = plla_outputs,
        .core_output = core_outputs,
+       .acr = 0x00020010UL,
 };
 
 static const struct clk_pll_characteristics upll_characteristics = {
@@ -131,6 +132,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
        .output = upll_outputs,
        .core_output = core_outputs,
        .upll = true,
+       .acr = 0x12023010UL, /* fIN = [18 MHz, 32 MHz]*/
 };
 
 /* Layout for fractional PLLs. */

diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
index ad9865feff02336607d72ec5435a5dcfe03a4e19..9ea253e6ff88eeea26e10e4a1337eb0e992df550 100644 (file)
--- a/drivers/clk/at91/sam9x7.c
+++ b/drivers/clk/at91/sam9x7.c
@@ -164,6 +164,7 @@ static const struct clk_pll_characteristics plla_characteristics = {
        .num_output = ARRAY_SIZE(plla_outputs),
        .output = plla_outputs,
        .core_output = plla_core_outputs,
+       .acr = 0x00020010UL, /* Old ACR_DEFAULT_PLLA value */
 };
 
 static const struct clk_pll_characteristics upll_characteristics = {
@@ -172,6 +173,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
        .output = upll_outputs,
        .core_output = upll_core_outputs,
        .upll = true,
+       .acr = 0x12023010UL, /* fIN=[20 MHz, 32 MHz] */
 };
 
 static const struct clk_pll_characteristics lvdspll_characteristics = {
@@ -179,6 +181,7 @@ static const struct clk_pll_characteristics lvdspll_characteristics = {
        .num_output = ARRAY_SIZE(lvdspll_outputs),
        .output = lvdspll_outputs,
        .core_output = lvdspll_core_outputs,
+       .acr = 0x12023010UL, /* fIN=[20 MHz, 32 MHz] */
 };
 
 static const struct clk_pll_characteristics audiopll_characteristics = {
@@ -186,6 +189,7 @@ static const struct clk_pll_characteristics audiopll_characteristics = {
        .num_output = ARRAY_SIZE(audiopll_outputs),
        .output = audiopll_outputs,
        .core_output = audiopll_core_outputs,
+       .acr = 0x12023010UL, /* fIN=[20 MHz, 32 MHz] */
 };
 
 static const struct clk_pll_characteristics plladiv2_characteristics = {
@@ -193,6 +197,7 @@ static const struct clk_pll_characteristics plladiv2_characteristics = {
        .num_output = ARRAY_SIZE(plladiv2_outputs),
        .output = plladiv2_outputs,
        .core_output = plladiv2_core_outputs,
+       .acr = 0x00020010UL,  /* Old ACR_DEFAULT_PLLA value */
 };
 
 /* Layout for fractional PLLs. */

diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c
index 8d2c25e6fa9d3cf855f2528b848a10edbcc0c71c..9f0b394543bf94c71645d3297bd6f6fbc23b4b4d 100644 (file)
--- a/drivers/clk/at91/sama7d65.c
+++ b/drivers/clk/at91/sama7d65.c
@@ -184,6 +184,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
        .num_output = ARRAY_SIZE(pll_outputs),
        .output = pll_outputs,
        .core_output = core_outputs,
+       .acr = 0x00070010UL,
 };
 
 /* Layout for fractional PLLs. */

diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index c0e27828b1acfcb1b2c8745902df56e335c22124..f24d251857fc9c647a41a1059ca9a0818dadd00c 100644 (file)
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -169,6 +169,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
        .num_output = ARRAY_SIZE(pll_outputs),
        .output = pll_outputs,
        .core_output = core_outputs,
+       .acr = 0x00070010UL,
 };
 
 /* Layout for fractional PLLs. */