]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
Xilinx: ARM: net: Make phy address configurable
authorJoe Hershberger <joe.hershberger@ni.com>
Tue, 21 Feb 2012 23:37:29 +0000 (17:37 -0600)
committerJagan <jaganna@xilinx.com>
Thu, 31 May 2012 07:39:48 +0000 (13:09 +0530)
Other boards my have different phy addresses.  Make it configurable.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
board/xilinx/dfe/xgmac.c
include/configs/xpele.h
include/configs/zynq_zc702.h
include/configs/zynq_zc770.h

index 93e36c07e47093b9587d04854d0b95d2961a873d..b70ca16c344a2c4537fb8955de5aa3250fac7534 100644 (file)
@@ -20,11 +20,6 @@ void set_eth_advertise(XEmacPss * EmacPssInstancePtr, int link_speed);
 /*************************** Constant Definitions ***************************/
 
 #define EMACPSS_DEVICE_ID   0
-#ifdef CONFIG_EP107
-# define PHY_ADDR 0x17
-#else
-# define PHY_ADDR 0x7
-#endif
 #define RXBD_CNT       8       /* Number of RxBDs to use */
 #define TXBD_CNT       8       /* Number of TxBDs to use */
 
@@ -72,7 +67,7 @@ static u32 phy_rd(XEmacPss * e, u32 a)
        u16 PhyData;
 
        phy_spinwait(e);
-       XEmacPss_PhyRead(e, PHY_ADDR, a, &PhyData);
+       XEmacPss_PhyRead(e, CONFIG_XGMAC_PHY_ADDR, a, &PhyData);
        phy_spinwait(e);
        return PhyData;
 }
@@ -80,7 +75,7 @@ static u32 phy_rd(XEmacPss * e, u32 a)
 static void phy_wr(XEmacPss * e, u32 a, u32 v)
 {
        phy_spinwait(e);
-       XEmacPss_PhyWrite(e, PHY_ADDR, a, v);
+       XEmacPss_PhyWrite(e, CONFIG_XGMAC_PHY_ADDR, a, v);
        phy_spinwait(e);
 }
 
index 2e9314aace019388f9ff1cdff34693cad41f0560..0334ee3b48717ee9275be1b809ec2eaa1da9b4ec 100644 (file)
 #define CONFIG_TTC0    1
 #define CONFIG_GEM0    1
 
+#ifdef CONFIG_EP107
+# define CONFIG_XGMAC_PHY_ADDR 0x17
+#else
+# define CONFIG_XGMAC_PHY_ADDR 0x7
+#endif
+
 #define TIMER_INPUT_CLOCK               XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / 2
 #define CONFIG_TIMER_PRESCALE           255
 #define TIMER_TICK_HZ                   (TIMER_INPUT_CLOCK / CONFIG_TIMER_PRESCALE)
index a8547dbe5e3e901f1a8982f215e9b12c14d60704..c4e8e31cd9192d0c709823e801ab9091ee4b239d 100644 (file)
 # define CONFIG_UART1  1
 #define CONFIG_TTC0    1
 #define CONFIG_GEM0    1
+#define CONFIG_XGMAC_PHY_ADDR 0x7
 
 #define TIMER_INPUT_CLOCK               XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / 2
 #define CONFIG_TIMER_PRESCALE           255
index a2cd976b60fcfa1d16156f9bcc15051d8193b78b..6789c1b0a86e3184a0b6da71185f99cc579b7da0 100644 (file)
 # define CONFIG_UART1  1
 #define CONFIG_TTC0    1
 #define CONFIG_GEM0    1
+#define CONFIG_XGMAC_PHY_ADDR 0x7
 
 #define TIMER_INPUT_CLOCK               XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / 2
 #define CONFIG_TIMER_PRESCALE           255