]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: rockchip: Add port subnodes to RK356x SATA controllers
authorHeiko Stuebner <heiko@sntech.de>
Sun, 1 Feb 2026 19:18:01 +0000 (20:18 +0100)
committerHeiko Stuebner <heiko@sntech.de>
Sun, 22 Feb 2026 22:28:49 +0000 (23:28 +0100)
The SATA controllers on RK356x are identical to the ones found on RK3588,
but don't yet provide a port sub-node. Per the datasheet the RK356x also
supports the fbscp capability and has the same queue maximums.

So add port sub-nodes to both sata controllers on RK356x, and move the
phy properties to it. Also add phandles to the ports, so that boards can
add their target-supply when available.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patch.msgid.link/20260201191804.41421-2-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi

index a2c4957a589921ee47fa98df11486443dd48ce58..68b48606f6010c95f89eadfe7814ec5b386e6156 100644 (file)
@@ -3,6 +3,7 @@
  * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
  */
 
+#include <dt-bindings/ata/ahci.h>
 #include <dt-bindings/clock/rk3568-cru.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
                         <&cru CLK_SATA1_RXOOB>;
                clock-names = "sata", "pmalive", "rxoob";
                interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-               phys = <&combphy1 PHY_TYPE_SATA>;
-               phy-names = "sata-phy";
                ports-implemented = <0x1>;
                power-domains = <&power RK3568_PD_PIPE>;
+               #address-cells = <1>;
+               #size-cells = <0>;
                status = "disabled";
+
+               sata1_port0: sata-port@0 {
+                       reg = <0>;
+                       hba-port-cap = <HBA_PORT_FBSCP>;
+                       phys = <&combphy1 PHY_TYPE_SATA>;
+                       phy-names = "sata-phy";
+                       snps,rx-ts-max = <32>;
+                       snps,tx-ts-max = <32>;
+               };
        };
 
        sata2: sata@fc800000 {
                         <&cru CLK_SATA2_RXOOB>;
                clock-names = "sata", "pmalive", "rxoob";
                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-               phys = <&combphy2 PHY_TYPE_SATA>;
-               phy-names = "sata-phy";
                ports-implemented = <0x1>;
                power-domains = <&power RK3568_PD_PIPE>;
+               #address-cells = <1>;
+               #size-cells = <0>;
                status = "disabled";
+
+               sata2_port0: sata-port@0 {
+                       reg = <0>;
+                       hba-port-cap = <HBA_PORT_FBSCP>;
+                       phys = <&combphy2 PHY_TYPE_SATA>;
+                       phy-names = "sata-phy";
+                       snps,rx-ts-max = <32>;
+                       snps,tx-ts-max = <32>;
+               };
        };
 
        usb_host0_xhci: usb@fcc00000 {