pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 SEL_I2C1 field width

[ Upstream commit 755a5b805fa7ff22e2934d67501efd92109f41ea ]

The SEL_I2C1 (MOD_SEL0[21:20]) field in Module Select Register 0 has a
width of 2 bits, i.e. it allows programming one out of 4 different
configurations.
However, the MOD_SEL0_21_20 macro contains 8 values instead of 4,
overflowing into the subsequent fields in the register, and thus breaking
the configuration of the latter.

Fix this by dropping the bogus last 4 values, including the non-existent
SEL_I2C1_4 configuration.

Fixes: 6d4036a1e3b3ac0f ("pinctrl: sh-pfc: Initial R8A77990 PFC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index b81c807ac54d52ed2719d83bf883043a81e133c3..d2fcf7f7b966829d78e329327c85029f05dbb805 100644 (file)
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -395,7 +395,7 @@ FM(IP12_31_28)      IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM
 #define MOD_SEL0_24            FM(SEL_HSCIF0_0)                FM(SEL_HSCIF0_1)
 #define MOD_SEL0_23            FM(SEL_HSCIF1_0)                FM(SEL_HSCIF1_1)
 #define MOD_SEL0_22            FM(SEL_HSCIF2_0)                FM(SEL_HSCIF2_1)
-#define MOD_SEL0_21_20         FM(SEL_I2C1_0)                  FM(SEL_I2C1_1)                  FM(SEL_I2C1_2)                  FM(SEL_I2C1_3)          FM(SEL_I2C1_4)          F_(0, 0)        F_(0, 0)        F_(0, 0)
+#define MOD_SEL0_21_20         FM(SEL_I2C1_0)                  FM(SEL_I2C1_1)                  FM(SEL_I2C1_2)                  FM(SEL_I2C1_3)
 #define MOD_SEL0_19_18_17      FM(SEL_I2C2_0)                  FM(SEL_I2C2_1)                  FM(SEL_I2C2_2)                  FM(SEL_I2C2_3)          FM(SEL_I2C2_4)          F_(0, 0)        F_(0, 0)        F_(0, 0)
 #define MOD_SEL0_16            FM(SEL_NDFC_0)                  FM(SEL_NDFC_1)
 #define MOD_SEL0_15            FM(SEL_PWM0_0)                  FM(SEL_PWM0_1)