arm64/sysreg: Add GICR CDNMIA encoding

The encoding for the GICR CDNMIA system instruction is thus far unused
(and shall remain unused for the time being). However, in order to
plumb the FGTs into KVM correctly, KVM needs to be made aware of the
encoding of this system instruction.

Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20260319154937.3619520-8-sascha.bischoff@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index f4436ecc630cd6b481f2123fbd901fdc8dc2da70..938cdb248f83ce67e24fe5f332229f1559a9db02 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1052,6 +1052,7 @@
 #define GICV5_OP_GIC_CDPRI             sys_insn(1, 0, 12, 1, 2)
 #define GICV5_OP_GIC_CDRCFG            sys_insn(1, 0, 12, 1, 5)
 #define GICV5_OP_GICR_CDIA             sys_insn(1, 0, 12, 3, 0)
+#define GICV5_OP_GICR_CDNMIA           sys_insn(1, 0, 12, 3, 1)
 
 /* Definitions for GIC CDAFF */
 #define GICV5_GIC_CDAFF_IAFFID_MASK    GENMASK_ULL(47, 32)
@@ -1098,6 +1099,12 @@
 #define GICV5_GIC_CDIA_TYPE_MASK       GENMASK_ULL(31, 29)
 #define GICV5_GIC_CDIA_ID_MASK         GENMASK_ULL(23, 0)
 
+/* Definitions for GICR CDNMIA */
+#define GICV5_GICR_CDNMIA_VALID_MASK   BIT_ULL(32)
+#define GICV5_GICR_CDNMIA_VALID(r)     FIELD_GET(GICV5_GICR_CDNMIA_VALID_MASK, r)
+#define GICV5_GICR_CDNMIA_TYPE_MASK    GENMASK_ULL(31, 29)
+#define GICV5_GICR_CDNMIA_ID_MASK      GENMASK_ULL(23, 0)
+
 #define gicr_insn(insn)                        read_sysreg_s(GICV5_OP_GICR_##insn)
 #define gic_insn(v, insn)              write_sysreg_s(v, GICV5_OP_GIC_##insn)