Revert "MIPS/testsuite: Use isa_rev=2 instead of >=2"

This reverts commit 10bb371eee6357cd32ffc8cfddcd62bd8b182c4b.

diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c
index c791575899920c90580500f50af945ecbbdd01a3..8caacb17d7a9856af52b259396ee4e13f4e53d92 100644 (file)
--- a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c
+++ b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev=2 -mmips16e2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */
 /* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
 
 /* Test cache.  */

diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
index 8d71e88596ccead166c967c27f96f99bf3eb71b5..a8a28a4d860061fc8744fdab9a18b785c82f0b34 100644 (file)
--- a/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
+++ b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev=2 -mmips16e2 -mbranch-cost=2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2 -mbranch-cost=2" } */
 /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
 
 /* Test MOVN.  */

diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-gp.c b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c
index 5fab454d5e06d5ce51b134772f40bc8c28d5fd5c..70d6230f017f590823c7368e185c12ade07350f7 100644 (file)
--- a/gcc/testsuite/gcc.target/mips/mips16e2-gp.c
+++ b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev=2 -mmips16e2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */
 /* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */
  
 /* Generate GP-relative ADDIU.  */

diff --git a/gcc/testsuite/gcc.target/mips/mips16e2.c b/gcc/testsuite/gcc.target/mips/mips16e2.c
index 33c4bb52ccca7c31493a7a4763d07f2a83789d1e..1b4b840bb4043138ed44cbd7e30d810339dc19c6 100644 (file)
--- a/gcc/testsuite/gcc.target/mips/mips16e2.c
+++ b/gcc/testsuite/gcc.target/mips/mips16e2.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev=2 -mmips16e2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */
 /* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */
  
 /* ANDI is a two operand instruction.  Hence, it won't be generated if src and