ARM: dts: renesas: r9a06g032: Describe the QSPI controller

Add a node describing the QSPI controller.
There are 2 clocks feeding this controller:
  - one for the reference clock
  - one that feeds both the ahb and the apb interfaces
As the binding expect either the ref clock, or all three (ref, ahb and
apb) clocks, it makes sense to provide the same clock twice.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20260205-schneider-6-19-rc1-qspi-v5-4-843632b3c674@bootlin.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index 0c6d6d8343954f61aadd86b651d618de2b08a10f..daa7d5de575dec77cf92f3b5038196a1960db63f 100644 (file)
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -101,6 +101,18 @@
                #size-cells = <1>;
                ranges;
 
+               qspi0: spi@40005000 {
+                       compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi";
+                       reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
+                       interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
+                                <&sysctrl R9A06G032_HCLK_QSPI0>;
+                       clock-names = "ref", "ahb", "apb";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                rtc0: rtc@40006000 {
                        compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
                        reg = <0x40006000 0x1000>;