clk: mediatek: pll: convert from round_rate() to determine_rate()

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index ce453e1718e5357e992d590fa174cbd1f061d5e1..139d3bfcf45f9ab094aa429e7b2913abaa3e29ea 100644 (file)
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -200,16 +200,19 @@ unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
        return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
 }
 
-long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
-                       unsigned long *prate)
+int mtk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
 {
        struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
        u32 pcw = 0;
        int postdiv;
 
-       mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
+       mtk_pll_calc_values(pll, &pcw, &postdiv, req->rate,
+                           req->best_parent_rate);
 
-       return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
+       req->rate = __mtk_pll_recalc_rate(pll, req->best_parent_rate, pcw,
+                                         postdiv);
+
+       return 0;
 }
 
 int mtk_pll_prepare(struct clk_hw *hw)
@@ -279,7 +282,7 @@ const struct clk_ops mtk_pll_ops = {
        .prepare        = mtk_pll_prepare,
        .unprepare      = mtk_pll_unprepare,
        .recalc_rate    = mtk_pll_recalc_rate,
-       .round_rate     = mtk_pll_round_rate,
+       .determine_rate = mtk_pll_determine_rate,
        .set_rate       = mtk_pll_set_rate,
 };
 

diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h
index 285c8db958b39e4cd30fe76f41a091806da9839e..670fa2e9b898c2ccb53da26e63b30552199fb6b5 100644 (file)
--- a/drivers/clk/mediatek/clk-pll.h
+++ b/drivers/clk/mediatek/clk-pll.h
@@ -96,8 +96,7 @@ void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
                         u32 freq, u32 fin);
 int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
                     unsigned long parent_rate);
-long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
-                       unsigned long *prate);
+int mtk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req);
 
 struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
                                        const struct mtk_pll_data *data,

diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pllfh.c
index 094ec8a26d66832d510dba94c96cb555f289ad27..83630ee07ee976bf980c8cf2dd35ea24c1b40821 100644 (file)
--- a/drivers/clk/mediatek/clk-pllfh.c
+++ b/drivers/clk/mediatek/clk-pllfh.c
@@ -42,7 +42,7 @@ static const struct clk_ops mtk_pllfh_ops = {
        .prepare        = mtk_pll_prepare,
        .unprepare      = mtk_pll_unprepare,
        .recalc_rate    = mtk_pll_recalc_rate,
-       .round_rate     = mtk_pll_round_rate,
+       .determine_rate = mtk_pll_determine_rate,
        .set_rate       = mtk_fhctl_set_rate,
 };