From 314b903c30040632db7edd187cd33003b2aee512 Mon Sep 17 00:00:00 2001
From: George Moussalem <george.moussalem@outlook.com>
Date: Fri, 16 May 2025 16:36:09 +0400
-Subject: dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC
+Subject: [PATCH] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC
The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
+ .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 +
include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
+ 2 files changed, 17 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h
-(limited to 'include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h')
-
+--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
++++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
+@@ -24,6 +24,7 @@ description:
+ properties:
+ compatible:
+ enum:
++ - qcom,ipq5018-cmn-pll
+ - qcom,ipq5424-cmn-pll
+ - qcom,ipq9574-cmn-pll
+
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h
@@ -0,0 +1,16 @@
--- /dev/null
+From a57666004f49fa5031d6bf388834213e6f961922 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Wed, 11 Mar 2026 19:39:38 +0100
+Subject: [PATCH] dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018
+
+The CMN PLL block in the IPQ6018 SoC takes 48 MHz as the reference
+input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
+bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
+subsystem.
+
+Add the related compatible for IPQ6018 to the ipq9574-cmn-pll
+generic schema.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
+Link: https://lore.kernel.org/r/20260311183942.10134-2-ansuelsmth@gmail.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 +
+ include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h | 15 +++++++++++++++
+ 2 files changed, 16 insertions(+)
+ create mode 100644 include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h
+
+--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
++++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
+@@ -26,6 +26,7 @@ properties:
+ enum:
+ - qcom,ipq5018-cmn-pll
+ - qcom,ipq5424-cmn-pll
++ - qcom,ipq6018-cmn-pll
+ - qcom,ipq9574-cmn-pll
+
+ reg:
+--- /dev/null
++++ b/include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
++ */
++
++#ifndef _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H
++#define _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H
++
++/* CMN PLL core clock. */
++#define IPQ6018_CMN_PLL_CLK 0
++
++/* The output clocks from CMN PLL of IPQ6018. */
++#define IPQ6018_BIAS_PLL_CC_CLK 1
++#define IPQ6018_BIAS_PLL_NSS_NOC_CLK 2
++#endif
--- /dev/null
+From 7156c65030006e6930dd99c5b8c5e84e69ca5f0b Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Wed, 11 Mar 2026 19:39:40 +0100
+Subject: [PATCH] dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074
+
+The CMN PLL block in the IPQ8074 SoC takes 48 MHz as the reference
+input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
+bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
+subsystem.
+
+Add the related compatible for IPQ8074 to the ipq9574-cmn-pll
+generic schema.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
+Link: https://lore.kernel.org/r/20260311183942.10134-4-ansuelsmth@gmail.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 +
+ include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h | 15 +++++++++++++++
+ 2 files changed, 16 insertions(+)
+ create mode 100644 include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h
+
+--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
++++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
+@@ -27,6 +27,7 @@ properties:
+ - qcom,ipq5018-cmn-pll
+ - qcom,ipq5424-cmn-pll
+ - qcom,ipq6018-cmn-pll
++ - qcom,ipq8074-cmn-pll
+ - qcom,ipq9574-cmn-pll
+
+ reg:
+--- /dev/null
++++ b/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
++ */
++
++#ifndef _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H
++#define _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H
++
++/* CMN PLL core clock. */
++#define IPQ8074_CMN_PLL_CLK 0
++
++/* The output clocks from CMN PLL of IPQ8074. */
++#define IPQ8074_BIAS_PLL_CC_CLK 1
++#define IPQ8074_BIAS_PLL_NSS_NOC_CLK 2
++#endif
+From 97eb2ac52726fbb702ced40d552a3f6f2683b664 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
-Date: Wed, 05 Mar 2026 12:00:00 +0100
-Subject: clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC support
+Date: Wed, 11 Mar 2026 19:39:39 +0100
+Subject: [PATCH] clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC support
The CMN PLL in IPQ6018 SoC supplies fixed clocks to the networking
subsystem: bias_pll_cc_clk at 300 MHz and bias_pll_nss_noc_clk at
416.5 MHz.
Signed-off-by: John Crispin <john@phrozen.org>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Link: https://lore.kernel.org/r/20260311183942.10134-3-ansuelsmth@gmail.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
- drivers/clk/qcom/ipq-cmn-pll.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
+ drivers/clk/qcom/ipq-cmn-pll.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
--- a/drivers/clk/qcom/ipq-cmn-pll.c
+++ b/drivers/clk/qcom/ipq-cmn-pll.c
static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = {
CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
-@@ -456,6 +463,7 @@ static const struct dev_pm_ops ipq_cmn_p
+@@ -449,6 +456,7 @@ static const struct dev_pm_ops ipq_cmn_p
static const struct of_device_id ipq_cmn_pll_clk_ids[] = {
{ .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks },
{ .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks },
+From 4e36f8ab45c406420f2c2ce6ee3988e0d13ba1c9 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
-Date: Wed, 05 Mar 2026 12:00:00 +0100
-Subject: clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
+Date: Wed, 11 Mar 2026 19:39:41 +0100
+Subject: [PATCH] clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
The CMN PLL in IPQ8074 SoC supplies fixed clocks to the networking
subsystem: bias_pll_cc_clk at 300 MHz and bias_pll_nss_noc_clk at
416.5 MHz.
Signed-off-by: John Crispin <john@phrozen.org>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Link: https://lore.kernel.org/r/20260311183942.10134-5-ansuelsmth@gmail.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
- drivers/clk/qcom/ipq-cmn-pll.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
+ drivers/clk/qcom/ipq-cmn-pll.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
--- a/drivers/clk/qcom/ipq-cmn-pll.c
+++ b/drivers/clk/qcom/ipq-cmn-pll.c
static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = {
CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
-@@ -464,6 +471,7 @@ static const struct of_device_id ipq_cmn
+@@ -457,6 +464,7 @@ static const struct of_device_id ipq_cmn
{ .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks },
{ .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks },
{ .compatible = "qcom,ipq6018-cmn-pll", .data = &ipq6018_output_clks },
+From 88c543fff756450bcd04ec4560c4440be36c9e75 Mon Sep 17 00:00:00 2001
From: Luo Jie <jie.luo@oss.qualcomm.com>
-Date: Tue, 06 Jan 2026 21:35:10 -0800
-Subject: [PATCH v2 1/5] clk: qcom: cmnpll: Account for reference clock divider
+Date: Tue, 6 Jan 2026 21:35:10 -0800
+Subject: [PATCH] clk: qcom: cmnpll: Account for reference clock divider
The clk_cmn_pll_recalc_rate() function must account for the reference clock
divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms
Fixes: f81715a4c87c ("clk: qcom: Add CMN PLL clock controller driver for IPQ SoC")
Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
+Tested-by: George Moussalem <george.moussalem@outlook.com>
+Link: https://lore.kernel.org/r/20260106-qcom_ipq5332_cmnpll-v2-1-f9f7e4efbd79@oss.qualcomm.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ drivers/clk/qcom/ipq-cmn-pll.c | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
--- a/drivers/clk/qcom/ipq-cmn-pll.c
+++ b/drivers/clk/qcom/ipq-cmn-pll.c
-@@ -186,7 +186,7 @@ static unsigned long clk_cmn_pll_recalc_
+@@ -200,7 +200,7 @@ static unsigned long clk_cmn_pll_recalc_
unsigned long parent_rate)
{
struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw);
/*
* The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted
-@@ -194,8 +194,15 @@ static unsigned long clk_cmn_pll_recalc_
+@@ -208,8 +208,15 @@ static unsigned long clk_cmn_pll_recalc_
*/
regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val);
factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val);
--- /dev/null
+From 02320d694fa1124b8b77fcb52191141004ef7fbb Mon Sep 17 00:00:00 2001
+From: George Moussalem <george.moussalem@outlook.com>
+Date: Thu, 21 May 2026 11:55:58 +0400
+Subject: arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate
+
+The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz.
+
+The CMN PLL driver did not account for the ref clock divider which is 2
+for IPQ5018. Therefore, the computed rate was twice the actual output.
+
+With the driver now accounting for the CMN PLL reference clock
+divider (commit: 88c543fff756), set the correct reference clock rate.
+
+Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node")
+Signed-off-by: George Moussalem <george.moussalem@outlook.com>
+Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
+Link: https://lore.kernel.org/r/20260521-ipq5018-cmn-pll-rate-fix-v2-1-04b28a92e0f2@outlook.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq5018.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi')
+
+--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+@@ -256,7 +256,7 @@
+ "sys";
+ #clock-cells = <1>;
+ assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;
+- assigned-clock-rates-u64 = /bits/ 64 <9600000000>;
++ assigned-clock-rates-u64 = /bits/ 64 <4800000000>;
+ };
+
+ qfprom: qfprom@a0000 {
+++ /dev/null
-From 5b00a1e17e98e99cc31b4dc6584b9ef93b8a62c4 Mon Sep 17 00:00:00 2001
-From: George Moussalem <george.moussalem@outlook.com>
-Date: Wed, 07 Jan 2026 18:21:49 +0400
-Subject: [PATCH] arm64: dts: qcom: ipq5018: fix assigned cmn-pll clock rate
-MIME-Version: 1.0
-Content-Type: text/plain; charset="utf-8"
-Content-Transfer-Encoding: 7bit
-Message-Id: <20260107-ipq5018-cmn-pll-rate-v1-6-9ab50c40cb32@outlook.com>
-
-In IPQ5018, the reference clock to the CMN PLL block from the on-board
-Wi-Fi has its divider set to 2. This divider wasn't taken into
-consideration when calculating the CMN PLL clock rate which meant the
-resulting clock rate was doubled.
-
-With the reference clock divider being accounted for in the driver,
-correct the assigned clock rate to 4.8GHz.
-
-Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node")
-Signed-off-by: George Moussalem <george.moussalem@outlook.com>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -269,7 +269,7 @@
- "sys";
- #clock-cells = <1>;
- assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;
-- assigned-clock-rates-u64 = /bits/ 64 <9600000000>;
-+ assigned-clock-rates-u64 = /bits/ 64 <4800000000>;
- };
-
- qfprom: qfprom@a0000 {
+++ /dev/null
-From: John Crispin <john@phrozen.org>
-Date: Wed, 05 Mar 2026 12:00:00 +0100
-Subject: dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018
-
-The CMN PLL block in the IPQ6018 SoC takes 48 MHz as the reference
-input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
-bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
-subsystem.
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
- create mode 100644 include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h
-
---- /dev/null
-+++ b/include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-+/*
-+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
-+ */
-+
-+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H
-+#define _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H
-+
-+/* CMN PLL core clock. */
-+#define IPQ6018_CMN_PLL_CLK 0
-+
-+/* The output clocks from CMN PLL of IPQ6018. */
-+#define IPQ6018_BIAS_PLL_CC_CLK 1
-+#define IPQ6018_BIAS_PLL_NSS_NOC_CLK 2
-+#endif
+++ /dev/null
-From: John Crispin <john@phrozen.org>
-Date: Wed, 05 Mar 2026 12:00:00 +0100
-Subject: dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074
-
-The CMN PLL block in the IPQ8074 SoC takes 48 MHz as the reference
-input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
-bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
-subsystem.
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
- create mode 100644 include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h
-
---- /dev/null
-+++ b/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-+/*
-+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
-+ */
-+
-+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H
-+#define _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H
-+
-+/* CMN PLL core clock. */
-+#define IPQ8074_CMN_PLL_CLK 0
-+
-+/* The output clocks from CMN PLL of IPQ8074. */
-+#define IPQ8074_BIAS_PLL_CC_CLK 1
-+#define IPQ8074_BIAS_PLL_NSS_NOC_CLK 2
-+#endif
projects / thirdparty / openwrt.git / commitdiff
