/*
* xqspips_init_hw - Initialize the hardware
- * @regs_base: Base address of QSPI controller
* @is_dual: Indicates whether dual memories are used
* @cs: Indicates which chip select is used in dual stacked
*
* - Set the little endian mode of TX FIFO and
* - Enable the QSPI controller
*/
-static void xqspips_init_hw(void __iomem *regs_base, int is_dual,
- unsigned int cs)
+static void xqspips_init_hw(int is_dual, unsigned int cs)
{
u32 config_reg;
}
/*
- * xqspips_irq - Interrupt service routine of the QSPI controller
+ * xqspips_irq_poll - Interrupt service routine of the QSPI controller
* @xqspi: Pointer to the xqspips structure
*
* This function handles TX empty and Mode Fault interrupts only.
* the SPI subsystem will identify the error as the remaining bytes to be
* transferred is non-zero.
*
- * returns: IRQ_HANDLED always
+ * returns: 0 for poll timeout
+ * 1 transfer operation complete
*/
static int xqspips_irq_poll(struct xqspips *xqspi)
{
*
* function will return -1, if there is no MIO configuration for
* qspi flash.
- *
- * @regs_base: base address of SLCR
*/
-
static int xqspips_check_is_dual_flash(void)
{
int is_dual = MODE_UNKNOWN;
return NULL;
}
- xqspips_init_hw((void *)XPSS_QSPI_BASEADDR, is_dual, cs);
+ xqspips_init_hw(is_dual, cs);
pspi = malloc(sizeof(struct zynq_spi_slave));
if (!pspi) {