arm64: dts: rockchip: Add USB nodes for RK3528

Rockchip RK3528 has one USB 3.0 DWC3 controller and oneUSB 2.0 EHCI/OHCI
controller and uses an Innosilicon-USB2PHY for USB 2.0. The DWC3
controller additionally uses the Naneng Combo PHY for USB3.

Add device tree nodes to describe these USB controllers along with the
USB 2.0 PHYs.

[moved snps,dis_u2_susphy_quirk here from individual boards,
 describe both usb2+3 default phy connections, usb2 boards can override]

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patch.msgid.link/20260529190355.4148175-2-heiko@sntech.de

diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index 77d314716b43bcf023bb4b5654832bfff24db87b..03cd00f88dbb6ba30ad446be0be4f5f7a9c6d10b 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -336,6 +336,33 @@
                        };
                };
 
+               usb_host0_xhci: usb@fe500000 {
+                       compatible = "rockchip,rk3528-dwc3", "snps,dwc3";
+                       reg = <0x0 0xfe500000 0x0 0x400000>;
+                       clocks = <&cru CLK_REF_USB3OTG>,
+                                <&cru CLK_SUSPEND_USB3OTG>,
+                                <&cru ACLK_USB3OTG>;
+                       clock-names = "ref_clk", "suspend_clk", "bus_clk";
+                       interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&power RK3528_PD_VPU>;
+                       resets = <&cru SRST_A_USB3OTG>;
+                       dr_mode = "otg";
+                       phys = <&usb2phy_otg>, <&combphy PHY_TYPE_USB3>;
+                       phy-names = "usb2-phy", "usb3-phy";
+                       phy_type = "utmi_wide";
+                       snps,dis_enblslpm_quirk;
+                       snps,dis_rxdet_inp3_quirk;
+                       snps,dis-del-phy-power-chg-quirk;
+                       snps,dis-tx-ipgap-linecheck-quirk;
+                       snps,dis-u1-entry-quirk;
+                       snps,dis-u2-entry-quirk;
+                       snps,dis-u2-freeclk-exists-quirk;
+                       snps,dis_u2_susphy_quirk;
+                       snps,parkmode-disable-hs-quirk;
+                       snps,parkmode-disable-ss-quirk;
+                       status = "disabled";
+               };
+
                gic: interrupt-controller@fed01000 {
                        compatible = "arm,gic-400";
                        reg = <0x0 0xfed01000 0 0x1000>,
@@ -349,6 +376,30 @@
                        #interrupt-cells = <3>;
                };
 
+               usb_host0_ehci: usb@ff100000 {
+                       compatible = "generic-ehci";
+                       reg = <0x0 0xff100000 0x0 0x40000>;
+                       clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
+                                <&usb2phy>;
+                       interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                       phys = <&usb2phy_host>;
+                       phy-names = "usb";
+                       power-domains = <&power RK3528_PD_VO>;
+                       status = "disabled";
+               };
+
+               usb_host0_ohci: usb@ff140000 {
+                       compatible = "generic-ohci";
+                       reg = <0x0 0xff140000 0x0 0x40000>;
+                       clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
+                                <&usb2phy>;
+                       interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+                       phys = <&usb2phy_host>;
+                       phy-names = "usb";
+                       power-domains = <&power RK3528_PD_VO>;
+                       status = "disabled";
+               };
+
                qos_crypto_a: qos@ff200000 {
                        compatible = "rockchip,rk3528-qos", "syscon";
                        reg = <0x0 0xff200000 0x0 0x20>;
@@ -1281,6 +1332,35 @@
                        rockchip,pipe-phy-grf = <&pipe_phy_grf>;
                        status = "disabled";
                };
+
+               usb2phy: usb2phy@ffdf0000 {
+                       compatible = "rockchip,rk3528-usb2phy";
+                       reg = <0x0 0xffdf0000 0x0 0x10000>;
+                       clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
+                       clock-names = "phyclk", "pclk";
+                       #clock-cells = <0>;
+                       clock-output-names = "clk_usbphy_480m";
+                       power-domains = <&power RK3528_PD_VO>;
+                       rockchip,usbgrf = <&vo_grf>;
+                       status = "disabled";
+
+                       usb2phy_otg: otg-port {
+                               interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "otg-bvalid", "otg-id",
+                                                 "linestate";
+                               #phy-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       usb2phy_host: host-port {
+                               interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "linestate";
+                               #phy-cells = <0>;
+                               status = "disabled";
+                       };
+               };
        };
 };