drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D

Xe3p_LPD has the same behavior as for Xe3_LPD with respect to DMC
context data for pipes C and D, which are lost when their power wells
are disabled.  As such, let's extend the condition for Xe3_LPD in
need_pipedmc_load_mmio() to also catch Xe3p_LPD.

Bspec: 68851
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-13-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 236674122428047520537eb704304617cf8285b7..6ebbd97e6351b2253af0ff3f637b3a9d5db783f7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -718,11 +718,11 @@ static bool need_pipedmc_load_program(struct intel_display *display)
 static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe)
 {
        /*
-        * PTL:
+        * Xe3_LPD/Xe3p_LPD:
         * - pipe A/B DMC doesn't need save/restore
         * - pipe C/D DMC is in PG0, needs manual save/restore
         */
-       if (DISPLAY_VER(display) == 30)
+       if (IS_DISPLAY_VER(display, 30, 35))
                return pipe >= PIPE_C;
 
        /*