drm/msm/a6xx: Add support for Debug HFI Q

Add the Debug HFI Queue which contains the F2H messages posted from the
GMU firmware. Having this data in coredump is useful to debug firmware
issues.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714666/
Message-ID: <20260327-a8xx-gpu-batch2-v2-7-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
index 0cd8ae1b4f5c82a1b79773fa445c833926cc3715..3f96b10b5f61a083e0beabcb4463530074f3345b 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
@@ -111,7 +111,7 @@ struct a6xx_gmu {
 
        unsigned long freq;
 
-       struct a6xx_hfi_queue queues[2];
+       struct a6xx_hfi_queue queues[HFI_MAX_QUEUES];
 
        bool initialized;
        bool hung;

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index 621f0b71ed11dacf90bb507de4c7dded07c34a05..4b51d6701aa27f039e99b2c6cc468a268910b6ef 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -57,7 +57,7 @@ struct a6xx_gpu_state {
        struct msm_gpu_state_bo *gmu_hfi;
        struct msm_gpu_state_bo *gmu_debug;
 
-       s32 hfi_queue_history[2][HFI_HISTORY_SZ];
+       s32 hfi_queue_history[HFI_MAX_QUEUES][HFI_HISTORY_SZ];
 
        struct list_head objs;
 

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
index 4f5dbf46132ba7d60a6277a38fce19fcd6cdda07..09b6bc464b47b8d7446e6fb42cd94f8ccbed8799 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
@@ -1062,8 +1062,8 @@ void a6xx_hfi_init(struct a6xx_gmu *gmu)
        struct a6xx_gmu_bo *hfi = &gmu->hfi;
        struct a6xx_hfi_queue_table_header *table = hfi->virt;
        struct a6xx_hfi_queue_header *headers = hfi->virt + sizeof(*table);
+       int table_size, idx;
        u64 offset;
-       int table_size;
 
        /*
         * The table size is the size of the table header plus all of the queue
@@ -1082,12 +1082,22 @@ void a6xx_hfi_init(struct a6xx_gmu *gmu)
        table->active_queues = ARRAY_SIZE(gmu->queues);
 
        /* Command queue */
+       idx = 0;
        offset = SZ_4K;
-       a6xx_hfi_queue_init(&gmu->queues[0], &headers[0], hfi->virt + offset,
+       a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset,
                hfi->iova + offset, 0);
 
        /* GMU response queue */
+       idx++;
        offset += SZ_4K;
-       a6xx_hfi_queue_init(&gmu->queues[1], &headers[1], hfi->virt + offset,
+       a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset,
                hfi->iova + offset, gmu->legacy ? 4 : 1);
+
+       /* GMU Debug queue */
+       idx++;
+       offset += SZ_4K;
+       a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset,
+               hfi->iova + offset, gmu->legacy ? 5 : 2);
+
+       WARN_ON(idx >= HFI_MAX_QUEUES);
 }

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h
index 6f9f74a0bc855f8a3e83c54303d5f3d6c8c7541d..19f6eca2c8c93b1fe2cecca33b754fc6b7ba3d43 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h
@@ -4,6 +4,8 @@
 #ifndef _A6XX_HFI_H_
 #define _A6XX_HFI_H_
 
+#define HFI_MAX_QUEUES 3
+
 struct a6xx_hfi_queue_table_header {
        u32 version;
        u32 size;               /* Size of the queue table in dwords */