gas/

	* config/tc-ppc.c (md_show_usage): Document -m476.
	* doc/c-ppc.texi (PowerPC-Opts): Document -m476.

gas/testsuite/
	* gas/ppc/476.s: New test.
	* gas/ppc/476.d: Likewise.
	* gas/ppc/ppc.exp: Run the 476 test.

include/opcode/
	* ppc.h (PPC_OPCODE_476): Define.

opcodes/
	* ppc-dis.c (ppc_opts): Add "476" entry.
	* ppc-opc.c (PPC476): Define.
	(powerpc_opcodes): Update mnemonics where required for 476.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d4c26ce5dade19d1f4bd4b37e0397f6ef724d5f3..3d85dd6140d2c3d34927fa7d84eab7613a4770e0 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
+
+       * config/tc-ppc.c (md_show_usage): Document -m476.
+       * doc/c-ppc.texi (PowerPC-Opts): Document -m476.
+
 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 
        * config/tc-ppc.c (md_show_usage): Rename "ppca2" to "a2".

diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 79d01018f88cd34f83e6ce26a521cf5f07361552..493bfe5546bd2a2b02663957955acd7ddfee0214 100644 (file)
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1188,6 +1188,7 @@ PowerPC options:\n\
 -m405                  generate code for PowerPC 405\n\
 -m440                  generate code for PowerPC 440\n\
 -m464                  generate code for PowerPC 464\n\
+-m476                  generate code for PowerPC 476\n\
 -m7400, -m7410, -m7450, -m7455\n\
                        generate code for PowerPC 7400/7410/7450/7455\n\
 -m750cl                        generate code for PowerPC 750cl\n"));

diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi
index 9e7972cc7e3b973c7512c1c47ac43ebdbbacfead..cab461b85ea4f8aae533771d23d5e7634c28e5e2 100644 (file)
--- a/gas/doc/c-ppc.texi
+++ b/gas/doc/c-ppc.texi
@@ -52,6 +52,9 @@ Generate code for PowerPC 403/405.
 @item -m440
 Generate code for PowerPC 440.  BookE and some 405 instructions.
 
+@item -m476
+Generate code for PowerPC 476.
+
 @item -m7400, -m7410, -m7450, -m7455
 Generate code for PowerPC 7400/7410/7450/7455.
 

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 55b6f3b2fd63d0e7482e9e8afdfe808878ad9f9d..694128f495d5f98491c696830c5aea92d0fc28c3 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
+
+       * gas/ppc/476.s: New test.
+       * gas/ppc/476.d: Likewise.
+       * gas/ppc/ppc.exp: Run the 476 test.
+
 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 
        * gas/ppc/a2.d: Rename "ppca2" to "a2".

diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 5c4af17619e3835eb3db823a131fa9c588b74c65..0c8d8527d6e395e02e58236bc4ca1c3c65417f75 100644 (file)
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -49,5 +49,6 @@ if { [istarget powerpc*-*-*] } then {
        run_dump_test "power6"
        run_dump_test "power7"
        run_dump_test "vsx"
+       run_dump_test "476"
     }
 }

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index c345d6bc4a01e6f26e0fdb3b5fdf4cf06f1e75ea..fad19ae9a6576393b0013a173dc320dd3da7b1ed 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
+
+       * ppc.h (PPC_OPCODE_476): Define.
+
 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 
        * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.

diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 4e147eb89dab2fc19f8f808792c46f6e57a5b224..eb8293d32dbf5f8919f48c119fb84eddf36f8de4 100644 (file)
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -168,7 +168,10 @@ extern const int powerpc_num_opcodes;
 #define PPC_OPCODE_VSX          0x80000000
 
 /* Opcode is supported by A2.  */
-#define PPC_OPCODE_A2          0x100000000ULL
+#define PPC_OPCODE_A2           0x100000000ULL
+
+/* Opcode is supported by PowerPC 476 processor.  */
+#define PPC_OPCODE_476          0x200000000ULL
 
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bbb214685e372ca84e52acf8f3ec963451695538..cf442bb4d6845ea5df73c70592f4de36329da761 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
+
+       * ppc-dis.c (ppc_opts): Add "476" entry.
+       * ppc-opc.c (PPC476): Define.
+       (powerpc_opcodes): Update mnemonics where required for 476.
+
 2009-10-02  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 
        * crx-dis.c (match_opcode): Truncate mcode to 32-bit.

diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 3af02bc9fbd007b6f6549ee3b2f77a2bd9332e25..ac88f7698eac2da4ccc8d4417a47191b6d0e4c46 100644 (file)
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -62,6 +62,10 @@ struct ppc_mopt ppc_opts[] = {
   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
                | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
     0 },
+  { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
+               | PPC_OPCODE_440 | PPC_OPCODE_476 | PPC_OPCODE_POWER4
+               | PPC_OPCODE_POWER5),
+    0 },
   { "601",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_601
                | PPC_OPCODE_32),
     0 },

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 4b1b9908ac78ca7166444cfc5b1d283044c60c6c..123436c4726c4fa8a166d80b9054456725aad576 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1906,6 +1906,7 @@ extract_dm (unsigned long insn,
 #define PPC405 PPC_OPCODE_405
 #define PPC440 PPC_OPCODE_440
 #define PPC464 PPC440
+#define PPC476 PPC_OPCODE_476
 #define PPC750 PPC
 #define PPC7450 PPC
 #define PPC860 PPC
@@ -1957,7 +1958,7 @@ extract_dm (unsigned long insn,
    constrained otherwise by disassembler operation.  */
 
 const struct powerpc_opcode powerpc_opcodes[] = {
-{"attn",       X(0,256),       X_MASK,   POWER4|PPCA2, PPCNONE,        {0}},
+{"attn",       X(0,256),       X_MASK,   POWER4|PPCA2, PPC476,         {0}},
 {"tdlgti",     OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
 {"tdllti",     OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
 {"tdeqi",      OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
@@ -2383,8 +2384,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhessf",   VX (4,1027),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"vand",       VX (4,1028),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpequb.",  VXR(4,   6,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi0fcm.",   APU(4, 515,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi0fcm",    APU(4, 515,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
+{"udi0fcm.",   APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi0fcm",    APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
 {"evmhossf",   VX (4,1031),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmheumi",   VX (4,1032),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmhesmi",   VX (4,1033),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
@@ -2410,8 +2411,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vavguh",     VX (4,1090),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vandc",      VX (4,1092),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpequh.",  VXR(4,  70,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi1fcm.",   APU(4, 547,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi1fcm",    APU(4, 547,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},   
+{"udi1fcm.",   APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi1fcm",    APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},   
 {"evmwhssf",   VX (4,1095),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwlumi",   VX (4,1096),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"vminfp",     VX (4,1098),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
@@ -2442,8 +2443,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vavguw",     VX (4,1154),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vor",                VX (4,1156),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpequw.",  VXR(4, 134,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi2fcm.",   APU(4, 579,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi2fcm",    APU(4, 579,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},   
+{"udi2fcm.",   APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi2fcm",    APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},   
 {"machhwsuo",  XO (4,  76,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"machhwsuo.", XO (4,  76,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"ps_merge10", XOPS(4,592,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
@@ -2456,8 +2457,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vxor",       VX (4,1220),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"evdivws",    VX (4,1222),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"vcmpeqfp.",  VXR(4, 198,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi3fcm.",   APU(4, 611,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi3fcm",    APU(4, 611,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},   
+{"udi3fcm.",   APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi3fcm",    APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},   
 {"evdivwu",    VX (4,1223),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evaddumiaaw",        VX (4,1224),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
 {"evaddsmiaaw",        VX (4,1225),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
@@ -2476,8 +2477,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhousiaaw",        VX (4,1284),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"vnor",       VX (4,1284),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"evmhossiaaw",        VX (4,1285),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
-{"udi4fcm.",   APU(4, 643,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi4fcm",    APU(4, 643,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
+{"udi4fcm.",   APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi4fcm",    APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
 {"evmhossfaaw",        VX (4,1287),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmheumiaaw",        VX (4,1288),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmhesmiaaw",        VX (4,1289),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
@@ -2496,8 +2497,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmwlusiaaw",        VX (4,1344),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwlssiaaw",        VX (4,1345),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"vavgsh",     VX (4,1346),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi5fcm.",   APU(4, 675,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi5fcm",    APU(4, 675,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
+{"udi5fcm.",   APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi5fcm",    APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
 {"evmwlumiaaw",        VX (4,1352),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwlsmiaaw",        VX (4,1353),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwssfaa",  VX (4,1363),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
@@ -2515,8 +2516,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmhessfanw",        VX (4,1411),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmhousianw",        VX (4,1412),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmhossianw",        VX (4,1413),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
-{"udi6fcm.",   APU(4, 707,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi6fcm",    APU(4, 707,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
+{"udi6fcm.",   APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi6fcm",    APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
 {"evmhossfanw",        VX (4,1415),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmheumianw",        VX (4,1416),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmhesmianw",        VX (4,1417),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
@@ -2535,8 +2536,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evmwlusianw",        VX (4,1472),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwlssianw",        VX (4,1473),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"vcmpgefp.",  VXR(4, 454,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi7fcm.",   APU(4, 739,0), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
-{"udi7fcm",    APU(4, 739,1), APU_MASK, PPC405|PPC440, PPCNONE,        {URT, URA, URB}},
+{"udi7fcm.",   APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
+{"udi7fcm",    APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
 {"evmwlumianw",        VX (4,1480),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwlsmianw",        VX (4,1481),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
 {"evmwssfan",  VX (4,1491),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
@@ -2550,48 +2551,48 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vsububs",    VX (4,1536),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"mfvscr",     VX (4,1540),    VX_MASK,     PPCVEC,    PPCNONE,        {VD}},
 {"vcmpgtub.",  VXR(4, 518,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi8fcm.",   APU(4, 771,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi8fcm",    APU(4, 771,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi8fcm.",   APU(4, 771,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi8fcm",    APU(4, 771,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"vsum4ubs",   VX (4,1544),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vsubuhs",    VX (4,1600),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"mtvscr",     VX (4,1604),    VX_MASK,     PPCVEC,    PPCNONE,        {VB}},
 {"vcmpgtuh.",  VXR(4, 582,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vsum4shs",   VX (4,1608),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi9fcm.",   APU(4, 804,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi9fcm",    APU(4, 804,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi9fcm.",   APU(4, 804,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi9fcm",    APU(4, 804,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"vsubuws",    VX (4,1664),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpgtuw.",  VXR(4, 646,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi10fcm.",  APU(4, 835,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi10fcm",   APU(4, 835,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi10fcm.",  APU(4, 835,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi10fcm",   APU(4, 835,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"vsum2sws",   VX (4,1672),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpgtfp.",  VXR(4, 710,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi11fcm.",  APU(4, 867,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi11fcm",   APU(4, 867,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi11fcm.",  APU(4, 867,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi11fcm",   APU(4, 867,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"vsubsbs",    VX (4,1792),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpgtsb.",  VXR(4, 774,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi12fcm.",  APU(4, 899,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi12fcm",   APU(4, 899,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi12fcm.",  APU(4, 899,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi12fcm",   APU(4, 899,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"vsum4sbs",   VX (4,1800),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"maclhwuo",   XO (4, 396,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"maclhwuo.",  XO (4, 396,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"vsubshs",    VX (4,1856),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpgtsh.",  VXR(4, 838,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi13fcm.",  APU(4, 931,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi13fcm",   APU(4, 931,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi13fcm.",  APU(4, 931,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi13fcm",   APU(4, 931,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"maclhwo",    XO (4, 428,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"maclhwo.",   XO (4, 428,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"nmaclhwo",   XO (4, 430,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"nmaclhwo.",  XO (4, 430,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"vsubsws",    VX (4,1920),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"vcmpgtsw.",  VXR(4, 902,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi14fcm.",  APU(4, 963,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi14fcm",   APU(4, 963,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi14fcm.",  APU(4, 963,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi14fcm",   APU(4, 963,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"vsumsws",    VX (4,1928),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
 {"maclhwsuo",  XO (4, 460,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"vcmpbfp.",   VXR(4, 966,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
-{"udi15fcm.",  APU(4, 995,0),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
-{"udi15fcm",   APU(4, 995,1),  APU_MASK,    PPC440,    PPCNONE,        {URT, URA, URB}},
+{"udi15fcm.",  APU(4, 995,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
+{"udi15fcm",   APU(4, 995,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"maclhwso",   XO (4, 492,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"maclhwso.",  XO (4, 492,1,1),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
 {"nmaclhwso",  XO (4, 494,1,0),XO_MASK, PPC405|PPC440, PPCNONE,        {RT, RA, RB}},
@@ -3150,11 +3151,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"crnot",      XL(19,33),      XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
 {"crnor",      XL(19,33),      XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
-{"rfmci",      X(19,38),   0xffffffff, PPCRFMCI|PPCA2, PPCNONE,        {0}},
+{"rfmci",      X(19,38),   0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
 
 {"rfdi",       XL(19,39),      0xffffffff,  E500MC,    PPCNONE,        {0}},
 {"rfi",                XL(19,50),      0xffffffff,  COM,       PPCNONE,        {0}},
-{"rfci",       XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2, PPCNONE, {0}},
+{"rfci",       XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
 
 {"rfsvc",      XL(19,82),      0xffffffff,  POWER,     PPCNONE,        {0}},
 
@@ -3174,7 +3175,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"crand",      XL(19,257),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
 
-{"hrfid",      XL(19,274),     0xffffffff, POWER5|CELL, PPCNONE,       {0}},
+{"hrfid",      XL(19,274),     0xffffffff, POWER5|CELL, PPC476,        {0}},
 
 {"crset",      XL(19,289),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
 {"creqv",      XL(19,289),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
@@ -3487,7 +3488,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"ldx",                X(31,21),       X_MASK,      PPC64,     PPCNONE,        {RT, RA0, RB}},
 
-{"icbt",       X(31,22),       X_MASK, BOOKE|PPCE300|PPCA2, PPCNONE,   {CT, RA, RB}},
+{"icbt",       X(31,22),       X_MASK, BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {CT, RA, RB}},
 
 {"lwzx",       X(31,23),       X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
 {"lx",         X(31,23),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
@@ -3593,7 +3594,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"ldarx",      X(31,84),       XEH_MASK,    PPC64,     PPCNONE,        {RT, RA0, RB, EH}},
 
-{"dcbfl",      XOPL(31,86,1),  XRT_MASK,    POWER5,    PPCNONE,        {RA, RB}},
+{"dcbfl",      XOPL(31,86,1),  XRT_MASK,    POWER5,    PPC476,         {RA, RB}},
 {"dcbf",       X(31,86),       XLRT_MASK,   PPC,       PPCNONE,        {RA, RB, L}},
 
 {"lbzx",       X(31,87),       X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
@@ -3626,9 +3627,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dcbfep",     XRT(31,127,0),  XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
 
-{"wrtee",      X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2, PPCNONE,     {RS}},
+{"wrtee",      X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}},
 
-{"dcbtstls",   X(31,134),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
+{"dcbtstls",   X(31,134),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
 
 {"stvebx",     X(31,135),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
 {"stbfcmx",    APU(31,135,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
@@ -3667,15 +3668,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"sle",                XRC(31,153,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
 {"sle.",       XRC(31,153,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
 
-{"prtyw",      X(31,154),      XRB_MASK, POWER6|PPCA2, PPCNONE,        {RA, RS}},
+{"prtyw",      X(31,154),      XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
 
 {"stdepx",     X(31,157),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
 
 {"stwepx",     X(31,159),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
 
-{"wrteei",     X(31,163), XE_MASK, PPC403|BOOKE|PPCA2, PPCNONE,        {E}},
+{"wrteei",     X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {E}},
 
-{"dcbtls",     X(31,166),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
+{"dcbtls",     X(31,166),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
 
 {"stvehx",     X(31,167),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
 {"sthfcmx",    APU(31,167,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
@@ -3731,7 +3732,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"stbepx",     X(31,223),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
 
-{"icblc",      X(31,230),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
+{"icblc",      X(31,230),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
 
 {"stvx",       X(31,231),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
 {"stqfcmx",    APU(31,231,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
@@ -3772,7 +3773,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dcbtstep",   XRT(31,255,0),  X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
 
-{"mfdcrx",     X(31,259),      X_MASK,   BOOKE|PPCA2,  PPCNONE,        {RS, RA}},
+{"mfdcrx",     X(31,259),      X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,    {RS, RA}},
 {"mfdcrx.",    XRC(31,259,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA}},
 
 {"icbt",       X(31,262),      XRT_MASK,    PPC403,    PPCNONE,        {RA, RB}},
@@ -3788,7 +3789,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"ehpriv",     X(31,270),      0xffffffff, E500MC|PPCA2, PPCNONE,      {0}},
 
-{"tlbiel",     X(31,274),      XRTLRA_MASK, POWER4,    PPCNONE,        {RB, L}},
+{"tlbiel",     X(31,274),      XRTLRA_MASK, POWER4,    PPC476,         {RB, L}},
 
 {"mfapidi",    X(31,275),      X_MASK,      BOOKE,     PPCNONE,        {RT, RA}},
 
@@ -3858,9 +3859,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfdmasa3",   XSPR(31,323,219), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
 {"mfdmacc3",   XSPR(31,323,220), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
 {"mfdmasr",    XSPR(31,323,224), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdcr",      X(31,323),      X_MASK, PPC403|BOOKE|PPCA2, PPCNONE,    {RT, SPR}},
+{"mfdcr",      X(31,323),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RT, SPR}},
 {"mfdcr.",     XRC(31,323,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, SPR}},
 
+{"dcread",     X(31,326),      X_MASK,      PPC476,    PPCNONE,        {RT, RA, RB}},
+
 {"div",                XO(31,331,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
 {"div.",       XO(31,331,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
 
@@ -4082,10 +4085,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"popcntw",    X(31,378),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
 
-{"mtdcrx",     X(31,387),      X_MASK,   BOOKE|PPCA2,  PPCNONE,        {RA, RS}},
+{"mtdcrx",     X(31,387),      X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,    {RA, RS}},
 {"mtdcrx.",    XRC(31,387,1),  X_MASK,      PPCA2,     PPCNONE,        {RA, RS}},
 
-{"dcblc",      X(31,390),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
+{"dcblc",      X(31,390),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
 {"stdfcmx",    APU(31,391,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
 
 {"divdeu",     XO(31,393,0,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
@@ -4161,11 +4164,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtdmasa3",   XSPR(31,451,219), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
 {"mtdmacc3",   XSPR(31,451,220), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
 {"mtdmasr",    XSPR(31,451,224), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdcr",      X(31,451),     X_MASK, PPC403|BOOKE|PPCA2, PPCNONE,     {SPR, RS}},
+{"mtdcr",      X(31,451),     X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {SPR, RS}},
 {"mtdcr.",     XRC(31,451,1), X_MASK,       PPCA2,     PPCNONE,        {SPR, RS}},
 
-{"dccci",      X(31,454),     XRT_MASK, PPC403|PPC440, PPCA2,          {RA, RB}},
-{"dci",                X(31,454),      XRARB_MASK,  PPCA2,     PPCNONE,        {CT}},
+{"dccci",      X(31,454),     XRT_MASK, PPC403|PPC440, PPCA2|PPC476,   {RA, RB}},
+{"dci",                X(31,454),      XRARB_MASK, PPCA2|PPC476, PPCNONE,      {CT}},
 
 {"divdu",      XO(31,457,0,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
 {"divdu.",     XO(31,457,0,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
@@ -4336,9 +4339,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dsn",        X(31,483),      XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
 
-{"dcread",     X(31,486),      X_MASK,  PPC403|PPC440, PPCA2,          {RT, RA, RB}},
+{"dcread",     X(31,486),      X_MASK,  PPC403|PPC440, PPCA2|PPC476,   {RT, RA, RB}},
 
-{"icbtls",     X(31,486),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
+{"icbtls",     X(31,486),      X_MASK, PPCCHLK|PPC476, PPCNONE,        {CT, RA, RB}},
 
 {"stvxl",      X(31,487),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
 
@@ -4359,7 +4362,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"popcntd",    X(31,506),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
 
-{"cmpb",       X(31,508),      X_MASK,   POWER6|PPCA2, PPCNONE,        {RA, RS, RB}},
+{"cmpb",       X(31,508),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {RA, RS, RB}},
 
 {"mcrxr",      X(31,512), XRARB_MASK|(3<<21), COM,     POWER7,         {BF}},
 
@@ -4437,8 +4440,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lwsync",     XSYNC(31,598,1), 0xffffffff, PPC,       PPCNONE,        {0}},
 {"ptesync",    XSYNC(31,598,2), 0xffffffff, PPC64,     PPCNONE,        {0}},
-{"sync",       X(31,598),      XSYNC_MASK,  PPCCOM,    BOOKE,          {LS}},
-{"msync",      X(31,598),      0xffffffff,  BOOKE|PPCA2, PPCNONE,      {0}},
+{"sync",       X(31,598),      XSYNC_MASK,  PPCCOM,    BOOKE|PPC476,   {LS}},
+{"msync",      X(31,598),      0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
 {"dcs",                X(31,598),      0xffffffff,  PWRCOM,    PPCNONE,        {0}},
 
 {"lfdx",       X(31,599),      X_MASK,      COM,       PPCNONE,        {FRT, RA0, RB}},
@@ -4565,7 +4568,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mullwo.",    XO(31,235,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
 {"mulso.",     XO(31,235,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
 
-{"dcba",       X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2, PPCNONE, {RA, RB}},
+{"dcba",       X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
 {"dcbal",      XOPL(31,758,1), XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
 
 {"stfdux",     X(31,759),      X_MASK,      COM,       PPCNONE,        {FRS, RAS, RB}},
@@ -4586,7 +4589,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lxvw4x",     X(31,780),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
 
-{"tlbivax",    X(31,786),      XRT_MASK,  BOOKE|PPCA2, PPCNONE,        {RA, RB}},
+{"tlbivax",    X(31,786),      XRT_MASK,  BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
 
 {"lwzcix",     X(31,789),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
 
@@ -4636,11 +4639,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lbzcix",     X(31,853),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
 
-{"eieio",      X(31,854),      0xffffffff,  PPC,       BOOKE|PPCA2,    {0}},
-{"mbar",       X(31,854),      X_MASK,   BOOKE|PPCA2,  PPCNONE,        {MO}},
-{"eieio",      X(31,854),      0xffffffff,  PPCA2,     PPCNONE,        {0}},
+{"eieio",      X(31,854),      0xffffffff,  PPC,   BOOKE|PPCA2|PPC476, {0}},
+{"mbar",       X(31,854),      X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,    {MO}},
+{"eieio",      X(31,854),      0xffffffff, PPCA2|PPC476, PPCNONE,      {0}},
 
-{"lfiwax",     X(31,855),      X_MASK,   POWER6|PPCA2, PPCNONE,        {FRT, RA0, RB}},
+{"lfiwax",     X(31,855),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, RA0, RB}},
 
 {"abso",       XO(31,360,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
 {"abso.",      XO(31,360,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
@@ -4662,8 +4665,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"stxvw4x",    X(31,908),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
 
-{"tlbsx",      XRC(31,914,0),  X_MASK, PPC403|BOOKE|PPCA2, PPCNONE,    {RTO, RA, RB}},
-{"tlbsx.",     XRC(31,914,1),  X_MASK, PPC403|BOOKE|PPCA2, PPCNONE,    {RTO, RA, RB}},
+{"tlbsx",      XRC(31,914,0),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
+{"tlbsx.",     XRC(31,914,1),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
 
 {"slbmfee",    X(31,915),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
 
@@ -4696,7 +4699,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"tlbrehi",    XTLB(31,946,0), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
 {"tlbrelo",    XTLB(31,946,1), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
-{"tlbre",      X(31,946),      X_MASK, PPC403|BOOKE|PPCA2, PPCNONE,    {RSO, RAOPT, SHO}},
+{"tlbre",      X(31,946),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
 
 {"sthcix",     X(31,949),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
 
@@ -4708,8 +4711,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"extsb",      XRC(31,954,0),  XRB_MASK,    PPC,       PPCNONE,        {RA, RS}},
 {"extsb.",     XRC(31,954,1),  XRB_MASK,    PPC,       PPCNONE,        {RA, RS}},
 
-{"iccci",      X(31,966),     XRT_MASK, PPC403|PPC440, PPCNONE,        {RA, RB}},
-{"ici",                X(31,966),      XRARB_MASK,  PPCA2,     PPCNONE,        {CT}},
+{"iccci",      X(31,966),     XRT_MASK, PPC403|PPC440, PPC476,         {RA, RB}},
+{"ici",                X(31,966),      XRARB_MASK,  PPCA2|PPC476, PPCNONE,     {CT}},
 
 {"divduo",     XO(31,457,1,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
 {"divduo.",    XO(31,457,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
@@ -4719,10 +4722,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"stxvd2x",    X(31,972),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
 
-{"tlbld",      X(31,978),      XRTRA_MASK,  PPC,   PPC403|BOOKE|PPCA2, {RB}},
+{"tlbld",      X(31,978),      XRTRA_MASK,  PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
 {"tlbwehi",    XTLB(31,978,0), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
 {"tlbwelo",    XTLB(31,978,1), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
-{"tlbwe",      X(31,978),      X_MASK, PPC403|BOOKE|PPCA2, PPCNONE,    {RSO, RAOPT, SHO}},
+{"tlbwe",      X(31,978),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
 
 {"stbcix",     X(31,981),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
 
@@ -4735,7 +4738,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"icbiep",     XRT(31,991,0),  XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
 
-{"icread",     X(31,998),     XRT_MASK, PPC403|PPC440, PPCNONE,        {RA, RB}},
+{"icread",     X(31,998),     XRT_MASK, PPC403|PPC440|PPC476, PPCNONE, {RA, RB}},
 
 {"nabso",      XO(31,488,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
 {"nabso.",     XO(31,488,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
@@ -4755,7 +4758,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dcbzep",     XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
 
-{"dcbzl",      XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPCNONE,      {RA, RB}},
+{"dcbzl",      XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476,       {RA, RB}},
 
 {"cctpl",      0x7c210b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
 {"cctpm",      0x7c421378,     0xffffffff,  CELL,      PPCNONE,        {0}},
@@ -4824,7 +4827,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"stfdu",      OP(55),         OP_MASK,     COM,       PPCNONE,        {FRS, D, RAS}},
 
-{"lq",         OP(56),         OP_MASK,     POWER4,    PPCNONE,        {RTQ, DQ, RAQ}},
+{"lq",         OP(56),         OP_MASK,     POWER4,    PPC476,         {RTQ, DQ, RAQ}},
 {"psq_l",      OP(56),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
 {"lfq",                OP(56),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
 
@@ -5097,7 +5100,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"std",                DSO(62,0),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RA0}},
 {"stdu",       DSO(62,1),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RAS}},
-{"stq",                DSO(62,2),      DS_MASK,     POWER4,    PPCNONE,        {RSQ, DS, RA0}},
+{"stq",                DSO(62,2),      DS_MASK,     POWER4,    PPC476,         {RSQ, DS, RA0}},
 
 {"fcmpu",      X(63,0),     X_MASK|(3<<21), COM,       PPCNONE,        {BF, FRA, FRB}},
 
@@ -5107,8 +5110,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dquaq",      ZRC(63,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
 {"dquaq.",     ZRC(63,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
 
-{"fcpsgn",     XRC(63,8,0),    X_MASK,   POWER6|PPCA2, PPCNONE,        {FRT, FRA, FRB}},
-{"fcpsgn.",    XRC(63,8,1),    X_MASK,   POWER6|PPCA2, PPCNONE,        {FRT, FRA, FRB}},
+{"fcpsgn",     XRC(63,8,0),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
+{"fcpsgn.",    XRC(63,8,1),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
 
 {"frsp",       XRC(63,12,0),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
 {"frsp.",      XRC(63,12,1),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
@@ -5217,10 +5220,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dcmpoq",     X(63,130),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
 
-{"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2, PPCNONE,   {BFF, U, W}},
-{"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2,                {BFF, U}},
-{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2, PPCNONE,   {BFF, U, W}},
-{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2,                {BFF, U}},
+{"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
+{"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
+{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
+{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
 
 {"fnabs",      XRC(63,136,0),  XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
 {"fnabs.",     XRC(63,136,1),  XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
@@ -5276,10 +5279,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dtstsfq",    X(63,674),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
 
-{"mtfsf",      XFL(63,711,0),  XFL_MASK, POWER6|PPCA2, PPCNONE,        {FLM, FRB, XFL_L, W}},
-{"mtfsf",      XFL(63,711,0),  XFL_MASK,    COM,       POWER6|PPCA2,   {FLM, FRB}},
-{"mtfsf.",     XFL(63,711,1),  XFL_MASK, POWER6|PPCA2, PPCNONE,        {FLM, FRB, XFL_L, W}},
-{"mtfsf.",     XFL(63,711,1),  XFL_MASK,    COM,       POWER6|PPCA2,   {FLM, FRB}},
+{"mtfsf",      XFL(63,711,0),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
+{"mtfsf",      XFL(63,711,0),  XFL_MASK,    COM, POWER6|PPCA2|PPC476,  {FLM, FRB}},
+{"mtfsf.",     XFL(63,711,1),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
+{"mtfsf.",     XFL(63,711,1),  XFL_MASK,    COM, POWER6|PPCA2|PPC476,  {FLM, FRB}},
 
 {"drdpq",      XRC(63,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
 {"drdpq.",     XRC(63,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
@@ -5288,16 +5291,22 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dcffixq.",   XRC(63,802,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
 
 {"fctid",      XRC(63,814,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
+{"fctid",      XRC(63,814,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
 {"fctid.",     XRC(63,814,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
+{"fctid.",     XRC(63,814,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
 
 {"fctidz",     XRC(63,815,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
+{"fctidz",     XRC(63,815,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
 {"fctidz.",    XRC(63,815,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
+{"fctidz.",    XRC(63,815,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
 
 {"denbcdq",    XRC(63,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
 {"denbcdq.",   XRC(63,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
 
 {"fcfid",      XRC(63,846,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
+{"fcfid",      XRC(63,846,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
 {"fcfid.",     XRC(63,846,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
+{"fcfid.",     XRC(63,846,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
 
 {"diexq",      XRC(63,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
 {"diexq.",     XRC(63,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},