bfd/RISC-V: Zvfbfwma implies Zvfbfmin

This is pretty clear from the spec.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c3cb4197ba800e99bb841605df14a12d9e2966d7..4f13976bb7e0206e6a9eac081035c0b122f16146 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1237,7 +1237,7 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvabd", "+zve32x", check_implicit_always},
   {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always},
   {"zvfhmin", "+zve32f", check_implicit_always},
-  {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
+  {"zvfbfwma", "+zfbfmin,+zvfbfmin", check_implicit_always},
   {"zvfbfmin", "+zve32f", check_implicit_always},
   {"zvfbdota32f", "+zve32f", check_implicit_always},
   {"zvfqwbdota8f", "+zve32f", check_implicit_always},

diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index 9fd6102a05633c87f068c0ea7447a1bcbb39aa42..2de5f2496000345d9cddd40c2b933381d659f19d 100644 (file)
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -27,7 +27,7 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0
-[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfwma1p0_zvl32b1p0
+[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0