ARM64: zynqmp: Enable SPI for zcu100

spi is bus 1, qspi is bus 0.

Example:
(Read max3107 ID)
ZynqMP> sspi 1:0.0 16 1f00
00A1
(Write gpio direction out - reg 18 - for all gpio pins)
ZynqMP> sspi 1:0.0 16 980f
0000
(Write value 1 (reg 19) for BT and WIFI (bit 0/bit 1)
ZynqMP> sspi 1:0.0 16 9903
0000

All write commands based on spec have 0x80 + reg address
as the first 8 bits.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_zcu100_defconfig b/configs/xilinx_zynqmp_zcu100_defconfig
index d3f6ef72445ffbc3e08bf680110ef30ff6beccf8..41f437c7204d75e777b73eb079fdd557a5bfc650 100644 (file)
--- a/configs/xilinx_zynqmp_zcu100_defconfig
+++ b/configs/xilinx_zynqmp_zcu100_defconfig
@@ -54,6 +54,7 @@ CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff010000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y