clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE

RK3528 comes with a new PLL variant: its "PPLL", which mainly generates
clocks for the PCIe controller, operates in normal mode only. Let's
describe it with flag ROCKCHIP_PLL_FIXED_MODE and handle it in code.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250217061142.38480-7-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index fe76756e592e9f1f25eb7af9948e3ae5b8a91ba0..2c2abb3b4210dffb4d5f9ac47d8999cc0c21f611 100644 (file)
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -204,10 +204,12 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
        rockchip_rk3036_pll_get_params(pll, &cur);
        cur.rate = 0;
 
-       cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
-       if (cur_parent == PLL_MODE_NORM) {
-               pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
-               rate_change_remuxed = 1;
+       if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {
+               cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
+               if (cur_parent == PLL_MODE_NORM) {
+                       pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
+                       rate_change_remuxed = 1;
+               }
        }
 
        /* update pll values */

diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 9b37d44b9e5d866e2f683177c6c59744cf309600..460de5a67faf7ec41f1d1615b7c9ab7db954d3ca 100644 (file)
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -444,6 +444,7 @@ struct rockchip_pll_rate_table {
  * Flags:
  * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
  *     rate_table parameters and ajust them if necessary.
+ * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only
  */
 struct rockchip_pll_clock {
        unsigned int            id;
@@ -461,6 +462,7 @@ struct rockchip_pll_clock {
 };
 
 #define ROCKCHIP_PLL_SYNC_RATE         BIT(0)
+#define ROCKCHIP_PLL_FIXED_MODE                BIT(1)
 
 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,  \
                _lshift, _pflags, _rtable)                              \