Trivial assertion fix -- the SSE3 instructions can be of size 8.

MERGE TO STABLE

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@1811

diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
index 282126604aea0abc361bbdd0cdc2af6b763906e2..a13537f799e07460294c924f9afc47cdd68d26dd 100644 (file)
--- a/memcheck/mc_translate.c
+++ b/memcheck/mc_translate.c
@@ -1089,7 +1089,7 @@ static UCodeBlock* memcheck_instrument ( UCodeBlock* cb_in )
             Bool is_load;
             Int t_size;
 
-            sk_assert(u_in->size == 4 || u_in->size == 16);
+            sk_assert(u_in->size == 4 || u_in->size == 8 || u_in->size == 16);
 
             t_size = INVALID_TEMPREG;
             is_load = u_in->opcode==SSE2a_MemRd