arm64: dts: apm: Clean-up clock bindings

Clean-up a couple of clock binding related issues in the the X-Gene DTS.

CPU and I2C nodes aren't clock providers and shouldn't have
"#clock-cells" properties.

A fixed-clock only provides 1 clock, so "#clock-cells" must be 0. The
preferred node name is "clock-<freq>" as well.

The "type" property is undocumented and unused, so drop it.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250910223020.612244-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index 5a64239b4708c397890985386ce4ec4db7eabe8b..b98fd434b7d638eefd1630a74646b0d9ef56bd9c 100644 (file)
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -22,7 +22,6 @@
                        enable-method = "spin-table";
                        cpu-release-addr = <0x1 0x0000fff8>;
                        next-level-cache = <&xgene_L2_0>;
-                       #clock-cells = <1>;
                        clocks = <&pmd0clk 0>;
                };
                cpu@1 {
@@ -32,7 +31,6 @@
                        enable-method = "spin-table";
                        cpu-release-addr = <0x1 0x0000fff8>;
                        next-level-cache = <&xgene_L2_0>;
-                       #clock-cells = <1>;
                        clocks = <&pmd0clk 0>;
                };
                cpu@100 {
@@ -42,7 +40,6 @@
                        enable-method = "spin-table";
                        cpu-release-addr = <0x1 0x0000fff8>;
                        next-level-cache = <&xgene_L2_1>;
-                       #clock-cells = <1>;
                        clocks = <&pmd1clk 0>;
                };
                cpu@101 {
@@ -52,7 +49,6 @@
                        enable-method = "spin-table";
                        cpu-release-addr = <0x1 0x0000fff8>;
                        next-level-cache = <&xgene_L2_1>;
-                       #clock-cells = <1>;
                        clocks = <&pmd1clk 0>;
                };
                cpu@200 {
@@ -62,7 +58,6 @@
                        enable-method = "spin-table";
                        cpu-release-addr = <0x1 0x0000fff8>;
                        next-level-cache = <&xgene_L2_2>;
-                       #clock-cells = <1>;
                        clocks = <&pmd2clk 0>;
                };
                cpu@201 {
@@ -72,7 +67,6 @@
                        enable-method = "spin-table";
                        cpu-release-addr = <0x1 0x0000fff8>;
                        next-level-cache = <&xgene_L2_2>;
-                       #clock-cells = <1>;
                        clocks = <&pmd2clk 0>;
                };
                cpu@300 {
@@ -82,7 +76,6 @@
                        enable-method = "spin-table";
                        cpu-release-addr = <0x1 0x0000fff8>;
                        next-level-cache = <&xgene_L2_3>;
-                       #clock-cells = <1>;
                        clocks = <&pmd3clk 0>;
                };
                cpu@301 {
@@ -92,7 +85,6 @@
                        enable-method = "spin-table";
                        cpu-release-addr = <0x1 0x0000fff8>;
                        next-level-cache = <&xgene_L2_3>;
-                       #clock-cells = <1>;
                        clocks = <&pmd3clk 0>;
                };
                xgene_L2_0: l2-cache-0 {
@@ -211,9 +203,9 @@
                };
        };
 
-       refclk: refclk {
+       refclk: clock-100000000 {
                compatible = "fixed-clock";
-               #clock-cells = <1>;
+               #clock-cells = <0>;
                clock-frequency = <100000000>;
                clock-output-names = "refclk";
        };
@@ -246,7 +238,7 @@
                        pmdpll: pmdpll@170000f0 {
                                compatible = "apm,xgene-pcppll-v2-clock";
                                #clock-cells = <1>;
-                               clocks = <&refclk 0>;
+                               clocks = <&refclk>;
                                reg = <0x0 0x170000f0 0x0 0x10>;
                                clock-output-names = "pmdpll";
                        };
@@ -286,7 +278,7 @@
                        socpll: socpll@17000120 {
                                compatible = "apm,xgene-socpll-v2-clock";
                                #clock-cells = <1>;
-                               clocks = <&refclk 0>;
+                               clocks = <&refclk>;
                                reg = <0x0 0x17000120 0x0 0x1000>;
                                clock-output-names = "socpll";
                        };

diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index 36214918190d734a5c33a8c845c9f9a54617717a..4ca0ead120c1d09925d8ce374295055fc738108b 100644 (file)
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -113,9 +113,9 @@
                interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
        };
 
-       refclk: refclk {
+       refclk: clock-100000000 {
                compatible = "fixed-clock";
-               #clock-cells = <1>;
+               #clock-cells = <0>;
                clock-frequency = <100000000>;
                clock-output-names = "refclk";
        };
@@ -159,28 +159,25 @@
                        pcppll: pcppll@17000100 {
                                compatible = "apm,xgene-pcppll-clock";
                                #clock-cells = <1>;
-                               clocks = <&refclk 0>;
+                               clocks = <&refclk>;
                                clock-names = "pcppll";
                                reg = <0x0 0x17000100 0x0 0x1000>;
                                clock-output-names = "pcppll";
-                               type = <0>;
                        };
 
                        socpll: socpll@17000120 {
                                compatible = "apm,xgene-socpll-clock";
                                #clock-cells = <1>;
-                               clocks = <&refclk 0>;
+                               clocks = <&refclk>;
                                clock-names = "socpll";
                                reg = <0x0 0x17000120 0x0 0x1000>;
                                clock-output-names = "socpll";
-                               type = <1>;
                        };
 
                        socplldiv2: socplldiv2  {
                                compatible = "fixed-factor-clock";
-                               #clock-cells = <1>;
+                               #clock-cells = <0>;
                                clocks = <&socpll 0>;
-                               clock-names = "socplldiv2";
                                clock-mult = <1>;
                                clock-div = <2>;
                                clock-output-names = "socplldiv2";
@@ -189,7 +186,7 @@
                        ahbclk: ahbclk@17000000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x17000000 0x0 0x2000>;
                                reg-names = "div-reg";
                                divider-offset = <0x164>;
@@ -201,7 +198,7 @@
                        sdioclk: sdioclk@1f2ac000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f2ac000 0x0 0x1000
                                        0x0 0x17000000 0x0 0x2000>;
                                reg-names = "csr-reg", "div-reg";
@@ -218,7 +215,7 @@
                        ethclk: ethclk {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                clock-names = "ethclk";
                                reg = <0x0 0x17000000 0x0 0x1000>;
                                reg-names = "div-reg";
@@ -240,7 +237,7 @@
                        sge0clk: sge0clk@1f21c000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f21c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                csr-mask = <0xa>;
@@ -251,7 +248,7 @@
                        xge0clk: xge0clk@1f61c000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f61c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                csr-mask = <0x3>;
@@ -262,7 +259,7 @@
                                compatible = "apm,xgene-device-clock";
                                status = "disabled";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f62c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                csr-mask = <0x3>;
@@ -272,7 +269,7 @@
                        sataphy1clk: sataphy1clk@1f21c000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f21c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "sataphy1clk";
@@ -286,7 +283,7 @@
                        sataphy2clk: sataphy1clk@1f22c000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f22c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "sataphy2clk";
@@ -300,7 +297,7 @@
                        sataphy3clk: sataphy1clk@1f23c000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f23c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "sataphy3clk";
@@ -314,7 +311,7 @@
                        sata01clk: sata01clk@1f21c000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f21c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "sata01clk";
@@ -327,7 +324,7 @@
                        sata23clk: sata23clk@1f22c000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f22c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "sata23clk";
@@ -340,7 +337,7 @@
                        sata45clk: sata45clk@1f23c000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f23c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "sata45clk";
@@ -353,7 +350,7 @@
                        rtcclk: rtcclk@17000000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x17000000 0x0 0x2000>;
                                reg-names = "csr-reg";
                                csr-offset = <0xc>;
@@ -366,7 +363,7 @@
                        rngpkaclk: rngpkaclk@17000000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x17000000 0x0 0x2000>;
                                reg-names = "csr-reg";
                                csr-offset = <0xc>;
@@ -380,7 +377,7 @@
                                status = "disabled";
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f2bc000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "pcie0clk";
@@ -390,7 +387,7 @@
                                status = "disabled";
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f2cc000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "pcie1clk";
@@ -400,7 +397,7 @@
                                status = "disabled";
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f2dc000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "pcie2clk";
@@ -410,7 +407,7 @@
                                status = "disabled";
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f50c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "pcie3clk";
@@ -420,7 +417,7 @@
                                status = "disabled";
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f51c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "pcie4clk";
@@ -429,7 +426,7 @@
                        dmaclk: dmaclk@1f27c000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f27c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "dmaclk";
@@ -850,7 +847,6 @@
                        compatible = "snps,designware-i2c";
                        reg = <0x0 0x10512000 0x0 0x1000>;
                        interrupts = <0 0x44 0x4>;
-                       #clock-cells = <1>;
                        clocks = <&ahbclk 0>;
                };