clk: rockchip: fix I2S1 clock gate register for rk3328

[ Upstream commit 5c73ac2f8b70834a603eb2d92eb0bb464634420b ]

This patch fixes definition of I2S1 clock gate register for rk3328.
Current setting is not related I2S clocks.
  - bit6 of CRU_CLKGATE_CON0 means clk_ddrmon_en
  - bit6 of CRU_CLKGATE_CON1 means clk_i2s1_en

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index ecbae8acd05b8c62b0048e8d5f07e39e86fc241c..f2f13b603ae9b811d4a8e52464c58c71ff153b1e 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -392,7 +392,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
                        RK3328_CLKGATE_CON(1), 5, GFLAGS,
                        &rk3328_i2s1_fracmux),
        GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
-                       RK3328_CLKGATE_CON(0), 6, GFLAGS),
+                       RK3328_CLKGATE_CON(1), 6, GFLAGS),
        COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,
                        RK3328_CLKSEL_CON(8), 12, 1, MFLAGS,
                        RK3328_CLKGATE_CON(1), 7, GFLAGS),