realtek: add support for ZyXEL GS1900-24E B1

The GS1900-24E B1 is a different hardware revision, not merely a
front-panel relabel as suggested by Zyxel's user guide. Verified
differences vs. A1 (sources: TechInfoDepot for A1 spec data,
https://techinfodepot.shoutwiki.com/wiki/ZyXEL_GS1900-24E):

* PCB: 37ZY-GM2430+212 V1.2 (A1: 37ZY-G724DO+412 V.12)
  - different board part number, not a stepping of the same one
* RAM: 128 MiB DDR3, A1: 128 MiB DDR2
* Flash: mx25l12805d, 16 MiB (A1: 16 MiB SPI-NOR)
* External PHYs: RTL8218D (A1: unknown)
* Rear power switch: absent on this B1 unit (inlet only). A1 is
  described as having one in the *title* of openwrt/openwrt#18620,
  but that issue does not explicitly identify the affected hardware
  as "A1" specifically, nor is it confirmed by a spec sheet or photo
* ZYXEL_VERS firmware family unchanged (AAHK)

The existing MDIO bus addressing and switch-port SerDes layout
from -a1.dts work unmodified on B1, since the PHY driver
identifies the external chip by ID registers at runtime rather
than from DT compatible string, regardless of what chip A1
actually uses.

Deliberately omits the gpio0 mdio-reset gpio-hog present in
-a1.dts (ba57225066, #18620) pending confirmation it's needed on
B1's differing reset-line topology. Tagged 802.1Q VLAN traffic
tested clean across software reboot and full AC power-cycle, on
both kernel 6.6/24.10.5 and current master (6.18), with no sign
of the #18620 stuck-RX regression.

Encapsulates the two external RTL8218D PHY packages per the tree-wide
ethernet-phy-package conversion for RTL8218x chips; ports 8-15 use the
SoC-integrated PHY block and aren't part of an external package.

Signed-off-by: Joshua Covington <joshuacov@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24377
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>

diff --git a/package/boot/uboot-tools/uboot-envtools/files/realtek b/package/boot/uboot-tools/uboot-envtools/files/realtek
index 4550719581302005b6ef712f6c8322827a875eb9..6a4e08b3ffb2f0d6c3a6528dd85298b798ef9e12 100644 (file)
--- a/package/boot/uboot-tools/uboot-envtools/files/realtek
+++ b/package/boot/uboot-tools/uboot-envtools/files/realtek
@@ -25,6 +25,7 @@ zyxel,gs1900-10hp-b1|\
 zyxel,gs1900-16-a1|\
 zyxel,gs1900-24-a1|\
 zyxel,gs1900-24e-a1|\
+zyxel,gs1900-24e-b1|\
 zyxel,gs1900-24ep-a1|\
 zyxel,gs1900-24hp-a1|\
 zyxel,gs1900-24hp-b1|\

diff --git a/target/linux/realtek/base-files/etc/board.d/02_network b/target/linux/realtek/base-files/etc/board.d/02_network
index ded5953e1df367056ddd65b28c85a8a10c5a683b..c07327a178fbcce2db3e81f7a6530779a06f6c80 100644 (file)
--- a/target/linux/realtek/base-files/etc/board.d/02_network
+++ b/target/linux/realtek/base-files/etc/board.d/02_network
@@ -145,6 +145,7 @@ realtek_setup_macs()
        zyxel,gs1900-24-a1|\
        zyxel,gs1900-24-b1|\
        zyxel,gs1900-24e-a1|\
+       zyxel,gs1900-24e-b1|\
        zyxel,gs1900-24ep-a1|\
        zyxel,gs1900-24hp-a1|\
        zyxel,gs1900-24hp-b1|\

diff --git a/target/linux/realtek/base-files/etc/board.d/05_compat-version b/target/linux/realtek/base-files/etc/board.d/05_compat-version
index 9ce0df27f0d789173ddc71d91cb14881930f6554..ab4c71905e2781a3d4534e7f97fe1b3ee11ffdad 100644 (file)
--- a/target/linux/realtek/base-files/etc/board.d/05_compat-version
+++ b/target/linux/realtek/base-files/etc/board.d/05_compat-version
@@ -21,6 +21,7 @@ case "$(board_name)" in
        zyxel,gs1900-10hp-b1 | \
        zyxel,gs1900-16-a1 | \
        zyxel,gs1900-24e-a1 | \
+       zyxel,gs1900-24e-b1 | \
        zyxel,gs1900-24ep-a1 | \
        zyxel,gs1900-24hp-a1 | \
        zyxel,gs1900-24hp-b1 | \

diff --git a/target/linux/realtek/dts/rtl8382_zyxel_gs1900-24e-b1.dts b/target/linux/realtek/dts/rtl8382_zyxel_gs1900-24e-b1.dts
new file mode 100644 (file)
index 0000000..2e9c647
--- /dev/null
+++ b/target/linux/realtek/dts/rtl8382_zyxel_gs1900-24e-b1.dts
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+#include "rtl8380_zyxel_gs1900_gpio.dtsi"
+
+/ {
+       compatible = "zyxel,gs1900-24e-b1", "realtek,rtl838x-soc";
+       model = "Zyxel GS1900-24E B1";
+};
+
+/*
+ * Unlike -a1.dts, this DTS deliberately does NOT hog gpio0 pin 1 to
+ * permanently de-assert the shared external-IC reset line (see
+ * commit ba57225066, "realtek: hog the GS1900-24E external IC reset
+ * line", and openwrt/openwrt#18620).
+ */
+
+&mdio_bus0 {
+       ethernet-phy-package@0 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0>;
+
+               PHY_C22(0, 0)
+               PHY_C22(1, 1)
+               PHY_C22(2, 2)
+               PHY_C22(3, 3)
+               PHY_C22(4, 4)
+               PHY_C22(5, 5)
+               PHY_C22(6, 6)
+               PHY_C22(7, 7)
+       };
+
+       ethernet-phy-package@16 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <16>;
+
+               PHY_C22(16, 16)
+               PHY_C22(17, 17)
+               PHY_C22(18, 18)
+               PHY_C22(19, 19)
+               PHY_C22(20, 20)
+               PHY_C22(21, 21)
+               PHY_C22(22, 22)
+               PHY_C22(23, 23)
+       };
+};
+
+&switch0 {
+       ethernet-ports {
+               SWITCH_PORT_SDS(1, 1, 0, 1, qsgmii)
+               SWITCH_PORT_SDS(0, 2, 0, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 3, 0, 3, qsgmii)
+               SWITCH_PORT_SDS(2, 4, 0, 2, qsgmii)
+               SWITCH_PORT_SDS(5, 5, 1, 1, qsgmii)
+               SWITCH_PORT_SDS(4, 6, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(7, 7, 1, 3, qsgmii)
+               SWITCH_PORT_SDS(6, 8, 1, 2, qsgmii)
+
+               SWITCH_PORT(9, 9, internal)
+               SWITCH_PORT(8, 10, internal)
+               SWITCH_PORT(11, 11, internal)
+               SWITCH_PORT(10, 12, internal)
+               SWITCH_PORT(13, 13, internal)
+               SWITCH_PORT(12, 14, internal)
+               SWITCH_PORT(15, 15, internal)
+               SWITCH_PORT(14, 16, internal)
+
+               SWITCH_PORT_SDS(17, 17, 2, 1, qsgmii)
+               SWITCH_PORT_SDS(16, 18, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(19, 19, 2, 3, qsgmii)
+               SWITCH_PORT_SDS(18, 20, 2, 2, qsgmii)
+               SWITCH_PORT_SDS(21, 21, 3, 1, qsgmii)
+               SWITCH_PORT_SDS(20, 22, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(23, 23, 3, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 24, 3, 2, qsgmii)
+       };
+};
+
+&gpio1 {
+       /delete-node/ poe_enable;
+};

diff --git a/target/linux/realtek/image/rtl838x.mk b/target/linux/realtek/image/rtl838x.mk
index 4e92c41eb7f0942fdab4a88a7785bb1daefe14be..4e52f83ad9887a48b9388b4ae034c09e54ef5767 100644 (file)
--- a/target/linux/realtek/image/rtl838x.mk
+++ b/target/linux/realtek/image/rtl838x.mk
@@ -488,6 +488,15 @@ define Device/zyxel_gs1900-24e-a1
 endef
 TARGET_DEVICES += zyxel_gs1900-24e-a1
 
+define Device/zyxel_gs1900-24e-b1
+  $(Device/zyxel_gs1900)
+  SOC := rtl8382
+  DEVICE_MODEL := GS1900-24E
+  DEVICE_VARIANT := B1
+  ZYXEL_VERS := AAHK
+endef
+TARGET_DEVICES += zyxel_gs1900-24e-b1
+
 define Device/zyxel_gs1900-24ep-a1
   $(Device/zyxel_gs1900)
   SOC := rtl8382