+++ /dev/null
-From eff2700d2ec99aac06fff0ad35cbc594bd3e04a8 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 10 Feb 2025 10:31:16 +0100
-Subject: [PATCH 1/2] ARM: dts: ixp4xx: Fix up PCI on WG302
-
-Looking at the board file for WG302 v2 was not a good idea
-because the GPIO IRQ for slot 2 differs, and v1 uses GPIO
-10 instead of GPIO 9. Fix it up.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/20250210-ixp4xx-dts-v1-2-6b752d745e04@linaro.org
----
- .../dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts
-+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts
-@@ -57,7 +57,7 @@
- status = "okay";
-
- /*
-- * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c)
-+ * Taken from WG302 v1 PCI boardfile (wg302v1-pci.c)
- * We have slots (IDSEL) 1 and 2 with one assigned IRQ
- * each handling all IRQs.
- */
-@@ -70,10 +70,10 @@
- <0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */
- <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
- /* IDSEL 2 */
-- <0x1000 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 9 */
-- <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
-- <0x1000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 9 */
-- <0x1000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 9 */
-+ <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
-+ <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */
-+ <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */
-+ <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */
- };
-
- ethernet@c8009000 {
+++ /dev/null
-From c9cc6b6a7d23eea7ada69a9185a550c4f0b62319 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 25 Jun 2025 08:51:25 +0200
-Subject: [PATCH] ARM: dts: Fix up wrv54g device tree
-
-Fix up the KS8995 switch and PHYs the way that is most likely:
-
-- Phy 1-4 is certainly the PHYs of the KS8995 (mask 0x1e in
- the outoftree code masks PHYs 1,2,3,4).
-- Phy 5 is the MII-P5 separate WAN phy of the KS8995 directly
- connected to EthC.
-- The EthB MII is probably connected as CPU interface to the
- KS8995.
-
-Properly integrate the KS8995 switch using the new bindings.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Link: https://patch.msgid.link/20250625-ks8995-dsa-bindings-v2-2-ce71dce9be0b@linaro.org
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- .../intel/ixp/intel-ixp42x-linksys-wrv54g.dts | 92 ++++++++++++++++---
- 1 file changed, 78 insertions(+), 14 deletions(-)
-
---- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
-+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
-@@ -72,10 +72,55 @@
- cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
- num-chipselects = <1>;
-
-- switch@0 {
-+ ethernet-switch@0 {
- compatible = "micrel,ks8995";
- reg = <0>;
- spi-max-frequency = <50000000>;
-+
-+ /*
-+ * The PHYs are accessed over the external MDIO
-+ * bus and not internally through the switch control
-+ * registers.
-+ */
-+ ethernet-ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ ethernet-port@0 {
-+ reg = <0>;
-+ label = "1";
-+ phy-mode = "mii";
-+ phy-handle = <&phy1>;
-+ };
-+ ethernet-port@1 {
-+ reg = <1>;
-+ label = "2";
-+ phy-mode = "mii";
-+ phy-handle = <&phy2>;
-+ };
-+ ethernet-port@2 {
-+ reg = <2>;
-+ label = "3";
-+ phy-mode = "mii";
-+ phy-handle = <&phy3>;
-+ };
-+ ethernet-port@3 {
-+ reg = <3>;
-+ label = "4";
-+ phy-mode = "mii";
-+ phy-handle = <&phy4>;
-+ };
-+ ethernet-port@4 {
-+ reg = <4>;
-+ ethernet = <ðb>;
-+ phy-mode = "mii";
-+ fixed-link {
-+ speed = <100>;
-+ full-duplex;
-+ };
-+ };
-+
-+ };
- };
- };
-
-@@ -135,40 +180,59 @@
- };
-
- /*
-- * EthB - connected to the KS8995 switch ports 1-4
-- * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to
-- * all four switch ports, also using an out of tree multiphy patch.
-- * Do we need a new binding and property for this?
-+ * EthB connects to the KS8995 CPU port and faces ports 1-4
-+ * through the switch fabric.
-+ *
-+ * To complicate things, the MDIO channel is also only
-+ * accessible through EthB, but used independently for PHY
-+ * control.
- */
-- ethernet@c8009000 {
-+ ethb: ethernet@c8009000 {
- status = "okay";
- queue-rx = <&qmgr 3>;
- queue-txready = <&qmgr 20>;
-- phy-mode = "rgmii";
-- phy-handle = <&phy4>;
-+ phy-mode = "mii";
-+ fixed-link {
-+ speed = <100>;
-+ full-duplex;
-+ };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
-- /* Should be ports 1-4 on the KS8995 switch */
-+ /*
-+ * LAN ports 1-4 on the KS8995 switch
-+ * and PHY5 for WAN need to be accessed
-+ * through this external MDIO channel.
-+ */
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ phy2: ethernet-phy@2 {
-+ reg = <2>;
-+ };
-+ phy3: ethernet-phy@3 {
-+ reg = <3>;
-+ };
- phy4: ethernet-phy@4 {
- reg = <4>;
- };
--
-- /* Should be port 5 on the KS8995 switch */
- phy5: ethernet-phy@5 {
- reg = <5>;
- };
- };
- };
-
-- /* EthC - connected to KS8995 switch port 5 */
-- ethernet@c800a000 {
-+ /*
-+ * EthC connects to MII-P5 on the KS8995 bypassing
-+ * all of the switch logic and facing PHY5
-+ */
-+ ethc: ethernet@c800a000 {
- status = "okay";
- queue-rx = <&qmgr 4>;
- queue-txready = <&qmgr 21>;
-- phy-mode = "rgmii";
-+ phy-mode = "mii";
- phy-handle = <&phy5>;
- };
- };
+++ /dev/null
-From 85ac6b806993200fe117f4fd047c74784ec6b515 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Fri, 22 Aug 2025 19:56:16 +0200
-Subject: [PATCH] ARM: dts: Add ixp4xx Actiontec MI424WR device trees
-
-The Actiontex MI424WR is a pretty widespread home router, made
-in many different revisions.
-
-Revisions A, C and D are based on IXP42x. We add a device tree
-for the A/C variant and one for the D variant as these differ in
-the location of the WAN PHY on the MDIO bus, and the ethernet
-interfaces for the WAN PHY and the DSA switch are switched around.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-3-cc804884474d@linaro.org
----
- arch/arm/boot/dts/intel/ixp/Makefile | 2 +
- .../ixp/intel-ixp42x-actiontec-mi424wr-ac.dts | 37 +++
- .../ixp/intel-ixp42x-actiontec-mi424wr-d.dts | 38 +++
- .../ixp/intel-ixp42x-actiontec-mi424wr.dtsi | 272 ++++++++++++++++++
- 4 files changed, 349 insertions(+)
- create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts
- create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts
- create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi
-
---- a/arch/arm/boot/dts/intel/ixp/Makefile
-+++ b/arch/arm/boot/dts/intel/ixp/Makefile
-@@ -1,5 +1,7 @@
- # SPDX-License-Identifier: GPL-2.0
- dtb-$(CONFIG_ARCH_IXP4XX) += \
-+ intel-ixp42x-actiontec-mi424wr-ac.dtb \
-+ intel-ixp42x-actiontec-mi424wr-d.dtb \
- intel-ixp42x-linksys-nslu2.dtb \
- intel-ixp42x-linksys-wrv54g.dtb \
- intel-ixp42x-freecom-fsg-3.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts
-@@ -0,0 +1,37 @@
-+// SPDX-License-Identifier: ISC
-+/*
-+ * Device Tree file for the IXP425-based Actiontec MI424WR revision A and C
-+ * Based on a board file from OpenWrt by Jose Vasconcellos.
-+ */
-+
-+/dts-v1/;
-+
-+#include "intel-ixp42x-actiontec-mi424wr.dtsi"
-+
-+/ {
-+ model = "Actiontec MI424WR rev A/C";
-+ compatible = "actiontec,mi424wr-ac", "intel,ixp42x";
-+
-+ soc {
-+ /* EthB used for WAN */
-+ ethernet@c8009000 {
-+ phy-handle = <&phy17>; // 17 on revision A-C
-+
-+ mdio {
-+ phy17: ethernet-phy@17 {
-+ /* WAN */
-+ reg = <17>;
-+ };
-+ };
-+ };
-+
-+ /* EthC used for LAN */
-+ ethernet@c800a000 {
-+ /* Fixed link to the CPU MII port on the KS8995 */
-+ fixed-link {
-+ speed = <100>;
-+ full-duplex;
-+ };
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts
-@@ -0,0 +1,38 @@
-+// SPDX-License-Identifier: ISC
-+/*
-+ * Device Tree file for the IXP425-based Actiontec MI424WR revision D
-+ * Based on a board file from OpenWrt by Jose Vasconcellos.
-+ */
-+
-+/dts-v1/;
-+
-+#include "intel-ixp42x-actiontec-mi424wr.dtsi"
-+
-+/ {
-+ model = "Actiontec MI424WR rev D";
-+ compatible = "actiontec,mi424wr-d", "intel,ixp42x";
-+
-+ soc {
-+ /* EthB used for LAN */
-+ ethernet@c8009000 {
-+ /* Fixed link to the CPU MII port on the KS8995 */
-+ fixed-link {
-+ speed = <100>;
-+ full-duplex;
-+ };
-+
-+ mdio {
-+ /* PHY ID 0x00221450 */
-+ phy5: ethernet-phy@5 {
-+ /* WAN */
-+ reg = <5>;
-+ };
-+ };
-+ };
-+
-+ /* EthC used for WAN */
-+ ethernet@c800a000 {
-+ phy-handle = <&phy5>; // 5 on revision D
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi
-@@ -0,0 +1,272 @@
-+// SPDX-License-Identifier: ISC
-+/*
-+ * Device Tree file for the IXP425-based Actiontec MI424WR
-+ * Based on a board file from OpenWrt by Jose Vasconcellos.
-+ */
-+
-+#include "intel-ixp42x.dtsi"
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-+
-+/ {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x00000000 0x02000000>;
-+ };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200n8";
-+ stdout-path = "uart1:115200n8";
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ led-wan-coax {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = "wan-coax";
-+ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
-+ default-state = "off";
-+ };
-+ led-power-alarm {
-+ color = <LED_COLOR_ID_RED>;
-+ function = LED_FUNCTION_ALARM;
-+ gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
-+ default-state = "off";
-+ };
-+ led-power {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_POWER;
-+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
-+ default-state = "on";
-+ linux,default-trigger = "heartbeat";
-+ };
-+ led-wireless {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_WLAN;
-+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ led-internet-down {
-+ color = <LED_COLOR_ID_RED>;
-+ function = "internet-down";
-+ gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
-+ default-state = "off";
-+ };
-+ led-internet-up {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = "internet-up";
-+ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
-+ default-state = "off";
-+ };
-+ led-lan-coax {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = "lan-coax";
-+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
-+ default-state = "off";
-+ };
-+ led-wan-ethernet-alarm {
-+ color = <LED_COLOR_ID_RED>;
-+ function = "wan-ethernet-alarm";
-+ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
-+ default-state = "off";
-+ };
-+ /* The last three LEDs are not mounted but traces exist on the PCB */
-+ led-phone-1 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = "phone-1";
-+ gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ led-phone-2 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = "phone-2";
-+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ led-voip {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = "voip";
-+ gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ };
-+
-+ gpio_keys {
-+ compatible = "gpio-keys";
-+
-+ button-reset {
-+ wakeup-source;
-+ linux,code = <KEY_RESTART>;
-+ label = "reset";
-+ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+
-+ spi {
-+ compatible = "spi-gpio";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ sck-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
-+ mosi-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
-+ miso-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
-+ cs-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
-+ num-chipselects = <1>;
-+
-+ ethernet-switch@0 {
-+ compatible = "micrel,ks8995";
-+ reg = <0>;
-+ spi-max-frequency = <50000000>;
-+
-+ ethernet-ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ ethernet-port@0 {
-+ reg = <0>;
-+ label = "lan1";
-+ phy-mode = "mii";
-+ phy-handle = <&phy1>;
-+ };
-+ ethernet-port@1 {
-+ reg = <1>;
-+ label = "lan2";
-+ phy-mode = "mii";
-+ phy-handle = <&phy2>;
-+ };
-+ ethernet-port@2 {
-+ reg = <2>;
-+ label = "lan3";
-+ phy-mode = "mii";
-+ phy-handle = <&phy3>;
-+ };
-+ ethernet-port@3 {
-+ reg = <3>;
-+ label = "lan4";
-+ phy-mode = "mii";
-+ phy-handle = <&phy4>;
-+ };
-+ ethernet-port@4 {
-+ reg = <4>;
-+ ethernet = <ðc>;
-+ phy-mode = "mii";
-+ fixed-link {
-+ speed = <100>;
-+ full-duplex;
-+ };
-+ };
-+
-+ };
-+ };
-+ };
-+
-+ soc {
-+ bus@c4000000 {
-+ flash@0,0 {
-+ compatible = "intel,ixp4xx-flash", "cfi-flash";
-+ bank-width = <2>;
-+ /*
-+ * 8 MB of Flash in 64 0x20000 sized blocks
-+ * mapped in at CS0.
-+ */
-+ reg = <0 0x00000000 0x0800000>;
-+
-+ /* Configure expansion bus to allow writes */
-+ intel,ixp4xx-eb-write-enable = <1>;
-+
-+ partitions {
-+ compatible = "redboot-fis";
-+ fis-index-block = <0x3f>;
-+ };
-+ };
-+ gpio1: gpio@1,0 {
-+ /* MMIO GPIO at CS1 */
-+ compatible = "intel,ixp4xx-expansion-bus-mmio-gpio";
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ big-endian;
-+ reg = <1 0x00000000 0x2>;
-+ reg-names = "dat";
-+ /* Expansion bus settings */
-+ intel,ixp4xx-eb-write-enable = <1>;
-+
-+ pci-reset-hog {
-+ gpio-hog;
-+ gpios = <7 GPIO_ACTIVE_HIGH>;
-+ output-high;
-+ line-name = "PCI reset";
-+ };
-+ pstn-relay-hog-1 {
-+ gpio-hog;
-+ gpios = <11 GPIO_ACTIVE_HIGH>;
-+ output-low;
-+ line-name = "PSTN relay control 1";
-+ };
-+ pstn-relay-hog-2 {
-+ gpio-hog;
-+ gpios = <12 GPIO_ACTIVE_HIGH>;
-+ output-low;
-+ line-name = "PSTN relay control 2";
-+ };
-+ };
-+ };
-+
-+ pci@c0000000 {
-+ status = "okay";
-+
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0xf800 0 0 7>;
-+ interrupt-map =
-+ /* IDSEL 13 */
-+ <0x6800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 8 */
-+ <0x6800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 6 */
-+ /* IDSEL 14 */
-+ <0x7000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
-+ <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 8 */
-+ /* IDSEL 15 */
-+ <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 6 */
-+ <0x7800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 15 is irq 7 */
-+ };
-+
-+ ethb: ethernet@c8009000 {
-+ status = "okay";
-+ queue-rx = <&qmgr 3>;
-+ queue-txready = <&qmgr 20>;
-+ phy-mode = "mii";
-+
-+ mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ /* 1, 2, 3 and 4 are ports on the KS8995 switch */
-+ phy1: ethernet-phy@1 {
-+ /* LAN1 */
-+ reg = <1>;
-+ };
-+ phy2: ethernet-phy@2 {
-+ /* LAN2 */
-+ reg = <2>;
-+ };
-+ phy3: ethernet-phy@3 {
-+ /* LAN3 */
-+ reg = <3>;
-+ };
-+ phy4: ethernet-phy@4 {
-+ /* LAN4 */
-+ reg = <4>;
-+ };
-+ };
-+ };
-+
-+ ethc: ethernet@c800a000 {
-+ status = "okay";
-+ queue-rx = <&qmgr 4>;
-+ queue-txready = <&qmgr 21>;
-+ phy-mode = "mii";
-+ };
-+ };
-+};
projects / thirdparty / openwrt.git / commitdiff
