drm/i915/display: Add missing clock to C10 PHY state compute/HW readout

Clock value is missing from C10 hw readout stage. Let's fix this.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20251015125446.3931198-8-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f8c1338f90539232ae7187bdfc969efa43c7cd3f..a74c1be225acd9c9461c95fb9c4a1c0a58563f7c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2103,6 +2103,9 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
        return 0;
 }
 
+static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
+                                       const struct intel_c10pll_state *pll_state);
+
 static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
                                          struct intel_c10pll_state *pll_state)
 {
@@ -2127,6 +2130,8 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
        pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0));
 
        intel_cx0_phy_transaction_end(encoder, wakeref);
+
+       pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
 }
 
 static void intel_c10_pll_program(struct intel_display *display,

diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
index 7fe6b4a18213327d8d41e07f5fe772d071cc4178..a201edceee1052e58cabc0cfb74f3707739c3db2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
@@ -332,6 +332,8 @@ void intel_snps_hdmi_pll_compute_c10pll(struct intel_c10pll_state *pll_state, u6
                              c10_curve_1, c10_curve_2, prescaler_divider,
                              &pll_params);
 
+       pll_state->clock = pixel_clock;
+
        pll_state->tx = 0x10;
        pll_state->cmn = 0x1;
        pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, pll_params.mpll_div5_en) |