* MA 02111-1307 USA
*/
#include <common.h>
-#include <linux/compiler.h>
+#include <asm/io.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
-__weak void lowlevel_init(void) {}
+void lowlevel_init(void)
+{
+ zynq_slcr_unlock();
+ /* remap DDR to zero, FILTERSTART */
+ writel(0, &scu_base->filter_start);
+
+ /* Device config APB, unlock the PCAP */
+ writel(0x757BDF0D, &devcfg_base->unlock);
+ writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
+
+ /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
+ writel(0x1F, &slcr_base->ocm_cfg);
+ /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
+ writel(0x0, &slcr_base->fpga_rst_ctrl);
+ /* TZ_DDR_RAM, Set DDR trust zone non-secure */
+ writel(0xFFFFFFFF, &slcr_base->trust_zone);
+ /* Set urgent bits with register */
+ writel(0x0, &slcr_base->ddr_urgent_sel);
+ /* Urgent write, ports S2/S3 */
+ writel(0xC, &slcr_base->ddr_urgent);
+
+ zynq_slcr_lock();
+}
void reset_cpu(ulong addr)
{
#define _ASM_ARCH_HARDWARE_H
#define XPSS_SYS_CTRL_BASEADDR 0xF8000000
+#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
+#define XPSS_SCU_BASEADDR 0xF8F00000
/* Reflect slcr offsets */
struct slcr_regs {
u32 slcr_unlock; /* 0x8 */
u32 reserved1[125];
u32 pss_rst_ctrl; /* 0x200 */
- u32 reserved2[21];
+ u32 reserved2[15];
+ u32 fpga_rst_ctrl; /* 0x240 */
+ u32 reserved3[5];
u32 reboot_status; /* 0x258 */
+ u32 boot_mode; /* 0x25c */
+ u32 reserved4[116];
+ u32 trust_zone; /* 0x430 */ /* FIXME */
+ u32 reserved5[115];
+ u32 ddr_urgent; /* 0x600 */
+ u32 reserved6[6];
+ u32 ddr_urgent_sel; /* 0x61c */
+ u32 reserved7[188];
+ u32 ocm_cfg; /* 0x910 */
};
#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
+struct devcfg_regs {
+ u32 ctrl; /* 0x0 */
+ u32 lock; /* 0x4 */
+ u32 cfg; /* 0x8 */
+ u32 int_sts; /* 0xc */
+ u32 int_mask; /* 0x10 */
+ u32 status; /* 0x14 */
+ u32 dma_src_addr; /* 0x18 */
+ u32 dma_dst_addr; /* 0x1c */
+ u32 dma_src_len; /* 0x20 */
+ u32 dma_dst_len; /* 0x24 */
+ u32 rom_shadow; /* 0x28 */
+ u32 reserved1[2];
+ u32 unlock; /* 0x34 */
+ u32 reserved2[18];
+ u32 mctrl; /* 0x80 */
+ u32 reserved3;
+ u32 write_count; /* 0x88 */
+ u32 read_count; /* 0x8c */
+};
+
+#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
+
+struct scu_regs {
+ u32 reserved1[16];
+ u32 filter_start; /* 0x40 */
+ u32 filter_end; /* 0x44 */
+};
+
+#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
+
#endif /* _ASM_ARCH_HARDWARE_H */
LIB = $(obj)lib$(BOARD).o
COBJS-y := board.o ../../xilinx/common/xbasic_types.o
-SOBJS := lowlevel_init.o
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include <asm/arch/nand.h>
#include <netdev.h>
#include <zynqpl.h>
+#include <asm/arch/hardware.h>
#define BOOT_MODE_REG (XPSS_SYS_CTRL_BASEADDR + 0x25C)
#define BOOT_MODES_MASK 0x0000000F
+++ /dev/null
-
-/*
- * This black box is a direct translation of init_ddrc.tcl.
- * The Zynq DDR controller is initialized herein.
- * It needs lots of love and attention some day.
- */
-
-#include <config.h>
-
-.globl lowlevel_init
-lowlevel_init:
-
- # unlock SLCR
- ldr r1, =(XPSS_SYS_CTRL_BASEADDR + 8)
- ldr r2, =0xDF0D
- str r2, [r1]
-
- # remap DDR to zero
- # FILTERSTART
- ldr r1, =(XPSS_SCU_BASEADDR + 0x40)
- ldr r2, =0
- str r2, [r1]
-
- # Device config APB
- # unlock the PCAP
- ldr r1, =(XPSS_DEV_CFG_APB_BASEADDR + 0x34)
- ldr r2, =0x757BDF0D
- str r2, [r1]
- ldr r1, =(XPSS_DEV_CFG_APB_BASEADDR + 0x28)
- ldr r2, =0xFFFFFFFF
- str r2, [r1]
-
- # OCM_CFG
- # Mask out the ROM
- # map ram into upper addresses
- ldr r1, =(XPSS_SYS_CTRL_BASEADDR +0x910)
- ldr r2, =0x1F
- str r2, [r1]
-
- # FPGA_RST_CTRL
- # clear resets on AXI fabric ports
- ldr r1, =(XPSS_SYS_CTRL_BASEADDR + 0x240)
- ldr r2, =0x0
- str r2, [r1]
-
- # TZ_DDR_RAM
- # Set DDR trust zone non-secure
- ldr r1, =(XPSS_SYS_CTRL_BASEADDR + 0x430)
- ldr r2, =0xFFFFFFFF
- str r2, [r1]
-
- # set urgent bits with register
- ldr r1, =(XPSS_SYS_CTRL_BASEADDR + 0x61C)
- ldr r2, =0
- str r2, [r1]
-
- # urgent write, ports S2/S3
- ldr r1, =(XPSS_SYS_CTRL_BASEADDR + 0x600)
- ldr r2, =0xC
- str r2, [r1]
-
- # relock SLCR
- ldr r1, =(XPSS_SYS_CTRL_BASEADDR + 0x4)
- ldr r2, =0x767B
- str r2, [r1]
-
- mov pc, lr
-
-doit:
- # Reset DDR controller
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0)
- ldr r2, =0x200
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x4)
- ldr r2, =0x000C1061
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0xC)
- ldr r2, =0x03001001
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x10)
- ldr r2, =0x00014001
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x14)
- ldr r2, =0x0004e020
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x18)
- ldr r2, =0x36264ccf
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x1C)
- ldr r2, =0x820158a4
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x20)
- ldr r2, =0x250882c4
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x28)
- ldr r2, =0x00809004
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x2C)
- ldr r2, =0x00000000
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x30)
- ldr r2, =0x00040952
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x34)
- ldr r2, =0x00020022
- str r2, [r1]
-
-#if (XPAR_MEMORY_MB_SIZE == 256)
-/*
- * starting with PEEP8 designs, there is 256 MB
- */
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x3C)
- ldr r2, =0x00000F88
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x40)
- ldr r2, =0xFF000000
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x44)
- ldr r2, =0x0FF66666
- str r2, [r1]
-#endif
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x50)
- ldr r2, =0x00000256
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x5C)
- ldr r2, =0x00002223
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x64)
- ldr r2, =0x00020FE0
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0xA4)
- ldr r2, =0x10200800
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0xB8)
- ldr r2, =0x00200065
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x17C)
- ldr r2, =0x00000050
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x180)
- ldr r2, =0x00000050
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x184)
- ldr r2, =0x00000050
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x188)
- ldr r2, =0x00000050
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x200)
- ldr r2, =0x00000000
- str r2, [r1]
-
- ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0x0)
- ldr r2, =0x201
- str r2, [r1]
-
-# Delay spin loop
- ldr r4, =0x1000000
-loop:
- sub r4, r4, #1
- cmp r4, #0
- bne loop
-
- mov pc, lr
-
#include <common.h>
#include <malloc.h>
#include <spi.h>
+#include <asm/arch/hardware.h>
#include "zynq_qspi.h"
/* FIXME this should be removed pretty soon */
#define XPSS_QSPI_BASEADDR 0xE000D000
-#define SD_BASEADDR 0xE0100000
#define XPSS_NAND_BASEADDR 0xE1000000
#define XPSS_CRTL_PARPORT_BASEADDR 0xE000E000
-
-#define RTL_30
-#ifdef RTL_30
-# define XPSS_QSPI_LIN_BASEADDR 0xFC000000
-# define XPSS_SYS_CTRL_BASEADDR 0xF8000000
-# define XPSS_DDR_CTRL_BASEADDR 0xF8006000
-# define XPSS_SCU_BASEADDR 0xF8F00000
-# define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
-#else
-# define XPSS_QSPI_LIN_BASEADDR 0xE6000000
-# define XPSS_SYS_CTRL_BASEADDR 0xFE000000
-# define XPSS_DDR_CTRL_BASEADDR 0xFE006000
-# define XPSS_SCU_BASEADDR 0xFEF00000
-# define XPSS_DEV_CFG_APB_BASEADDR 0xFE007000
-#endif
+#define SD_BASEADDR 0xE0100000
+#define XPSS_QSPI_LIN_BASEADDR 0xFC000000
#endif /* __CONFIG_ZYNQ_COMMON_H */
projects / thirdparty / u-boot.git / commitdiff
