PCI: mediatek-gen3: Split out device power helpers

In preparation for adding full power on/off control with the pwrctrl API,
split out the existing code that only partially deals with device power
sequencing into separate helper functions. The existing code only handles
PERST#.

This is purely moving code around, and brings no functional changes.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
[mani: moved the 'err' variable to next commit]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20260324052002.4072430-6-wenst@chromium.org

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 22a16e4ebc761c0d4cb9d34e3bcc84c5d31334ed..436dbd925181ba666d269f224a7766c0e16f5413 100644 (file)
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -403,6 +403,53 @@ static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie)
        writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
 }
 
+static int mtk_pcie_devices_power_up(struct mtk_gen3_pcie *pcie)
+{
+       u32 val;
+
+       /*
+        * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal
+        * causing occasional PCIe link down. In order to overcome the issue,
+        * PCIE_RSTB signals are not asserted/released at this stage and the
+        * PCIe block is reset using en7523_reset_assert() and
+        * en7581_pci_enable().
+        */
+       if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
+               /* Assert all reset signals */
+               val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
+               val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
+                      PCIE_PE_RSTB;
+               writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
+
+               /*
+                * Described in PCIe CEM specification revision 6.0.
+                *
+                * The deassertion of PERST# should be delayed 100ms (TPVPERL)
+                * for the power and clock to become stable.
+                */
+               msleep(PCIE_T_PVPERL_MS);
+
+               /* De-assert reset signals */
+               val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
+                        PCIE_PE_RSTB);
+               writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
+       }
+
+       return 0;
+}
+
+static void mtk_pcie_devices_power_down(struct mtk_gen3_pcie *pcie)
+{
+       u32 val;
+
+       if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
+               /* Assert the PERST# pin */
+               val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
+               val |= PCIE_PE_RSTB;
+               writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
+       }
+}
+
 static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
 {
        struct resource_entry *entry;
@@ -489,33 +536,9 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
                        return err;
        }
 
-       /*
-        * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal
-        * causing occasional PCIe link down. In order to overcome the issue,
-        * PCIE_RSTB signals are not asserted/released at this stage and the
-        * PCIe block is reset using en7523_reset_assert() and
-        * en7581_pci_enable().
-        */
-       if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
-               /* Assert all reset signals */
-               val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
-               val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
-                      PCIE_PE_RSTB;
-               writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
-
-               /*
-                * Described in PCIe CEM specification revision 6.0.
-                *
-                * The deassertion of PERST# should be delayed 100ms (TPVPERL)
-                * for the power and clock to become stable.
-                */
-               msleep(PCIE_T_PVPERL_MS);
-
-               /* De-assert reset signals */
-               val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
-                        PCIE_PE_RSTB);
-               writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
-       }
+       err = mtk_pcie_devices_power_up(pcie);
+       if (err)
+               return err;
 
        /* Check if the link is up or not */
        err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
@@ -1270,7 +1293,6 @@ static int mtk_pcie_suspend_noirq(struct device *dev)
 {
        struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
        int err;
-       u32 val;
 
        /* Trigger link to L2 state */
        err = mtk_pcie_turn_off_link(pcie);
@@ -1279,13 +1301,7 @@ static int mtk_pcie_suspend_noirq(struct device *dev)
                return err;
        }
 
-       if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
-               /* Assert the PERST# pin */
-               val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
-               val |= PCIE_PE_RSTB;
-               writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
-       }
-
+       mtk_pcie_devices_power_down(pcie);
        dev_dbg(pcie->dev, "entered L2 states successfully");
 
        mtk_pcie_irq_save(pcie);