This commit only updates xparameters*.h from the standalone BSP.
Testing was not done with only this commit as this was done for flash
testing such that the following commits for flash were also used
together with this one.
+++ /dev/null
-/*
- * flash.c: Support code for the flash chips on the Xilinx PELE board
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire program
- * is licensed under the GPL.
- *
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <configs/xpele.h>
-#include "pl353_x8.h"
-
-#ifndef CONFIG_SYS_NO_FLASH
-
-#define FLASH_BANK_SIZE (16*1024*1024) //16MB
-#define FLASH_SIZE CONFIG_SYS_FLASH_SIZE
-#define SECT_SIZE (64*1024) //a.k.a BLOCK_SIZE
-#define PAGE_SIZE 32
-
-#define FLASH_STATUS_DONE 0x80
-#define FLASH_STATUS_ESS 0x40
-#define FLASH_STATUS_ECLBS 0x20
-#define FLASH_STATUS_PSLBS 0x10
-#define FLASH_STATUS_VPENS 0x08
-#define FLASH_STATUS_PSS 0x04
-#define FLASH_STATUS_DPS 0x02
-#define FLASH_STATUS_PROTECT 0x01
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static int flash_full_status_check(ulong addr);
-
-static initialize = 0;
-
-ulong flash_init(void)
-{
-
- int i, j;
- ulong size = 0;
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- ulong flashbase = 0;
-
- flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) |
- (INTEL_ID_28F256P30T & FLASH_TYPEMASK);
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- memset(flash_info[i].protect, 1, CONFIG_SYS_MAX_FLASH_SECT);
- if (i == 0)
- flashbase = CONFIG_SYS_FLASH_BASE;
-
- for (j = 0; j < flash_info[i].sector_count; j++)
- flash_info[i].start[j] = flashbase + j * SECT_SIZE;
-
- size += flash_info[i].size;
- }
-
- return size;
-}
-
-int do_flinit(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- if (initialize) {
- printf("FLASH already initialized\r\n");
- return 1;
- }
- initialize = 1;
- printf("FLASH Initialized\r\n");
- init_nor_flash();
- return 0;
-}
-
-U_BOOT_CMD(flinit, 1, 0, do_flinit,
- "FLASH memory initialization",
- "\n - flinit initialize the FLASH memory\n"
- "flinit \n - initialize the FLASH ");
-
-void flash_print_info(flash_info_t * info)
-{
-
- int i;
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case (INTEL_MANUFACT & FLASH_VENDMASK):
- printf("Intel: ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case (INTEL_ID_28F256P30T & FLASH_TYPEMASK):
- printf("INTEL_ID_28F256P30T 16MByte)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- printf(" Size: %ld MB in %d Sectors\n", info->size >> 20,
- info->sector_count);
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf("\n");
-}
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
-
- int rc = ERR_OK;
- int sect;
-
- if (!initialize) {
- printf("FLASH not initialized. Use flinit command. \r\n");
- return ERR_UNKNOWN_FLASH_TYPE;
- }
- if (info->flash_id == FLASH_UNKNOWN)
- return ERR_UNKNOWN_FLASH_TYPE;
-
- if ((s_first < 0) || (s_first > s_last))
- return ERR_INVAL;
-
- if ((info->flash_id & FLASH_VENDMASK) !=
- (INTEL_MANUFACT & FLASH_VENDMASK))
- return ERR_UNKNOWN_FLASH_VENDOR;
-
- for (sect = s_first; sect <= s_last; ++sect)
- if (info->protect[sect]) {
- printf("Flash is protected.\n");
- return ERR_PROTECTED;
- }
- printf("\n");
- for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
- volatile unsigned long long *addr =
- (unsigned long long *)(info->start[sect]);
-
- printf("Erasing sector %d ... \n", sect);
- block_erase_nor_flash((u32) addr);
- rc = flash_full_status_check(info->start[sect]);
- }
-
- if (ctrlc())
- printf("User Interrupt!\n");
-
- return rc;
-}
-
-int flash_real_protect(flash_info_t * info, long sector, int prot)
-{
-
- if (!initialize) {
- printf("FLASH not initialized. Use flinit command. \r\n");
- return ERR_UNKNOWN_FLASH_TYPE;
- }
- int retcode = 0;
- if (prot)
- lock_nor_flash(info->start[sector]);
- else
- unlock_nor_flash(info->start[sector]);
-
- info->protect[sector] = prot;
- retcode = flash_full_status_check(info->start[sector]);
- return retcode;
-}
-
-static int flash_full_status_check(ulong addr)
-{
- int retcode;
- retcode = read_status_reg_nor_flash(addr);
- if (retcode != FLASH_STATUS_DONE) {
- printf("\nFlash error at address %lx with retcode=0x%x\n", addr,
- retcode);
- if (retcode & (FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS))
- printf("Command Sequence Error.\n");
- else if (retcode & FLASH_STATUS_ECLBS)
- printf("Block Erase Error.\n");
- else if (retcode & FLASH_STATUS_PSLBS)
- printf("Locking Error\n");
- if (retcode & FLASH_STATUS_DPS)
- printf("Block locked.\n");
- if (retcode & FLASH_STATUS_VPENS)
- printf("Vpp Low Error.\n");
- retcode = 1;
- } else
- retcode = 0;
-
- Xil_Out8(addr, 0xFF);
- return retcode;
-}
-
-static int write_word(flash_info_t * info, ulong dest, unsigned long data)
-{
-
- volatile unsigned char *addr1 = (unsigned char *)dest;
- volatile unsigned long *addr2 = (unsigned long *)dest;
- unsigned long result;
- int rc = ERR_OK;
- int i;
- char real_data;
- result = *addr2;
- if ((result & data) != data)
- return ERR_NOT_ERASED;
- for (i = 0; i < 4; i++) {
- real_data = (data >> (i * 8)) & 0xFF;
- write_byte_nor_flash((u32) (addr1 + i), real_data);
- }
- rc = flash_full_status_check((u32) addr1);
- return rc;
-
-}
-
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-
- if (!initialize) {
- printf("FLASH not initialized. Use flinit command. \r\n");
- return ERR_UNKNOWN_FLASH_TYPE;
- }
-#if CONFIG_SYS_FLASH_USE_BUFFER_WRITE
- ulong pages, remain;
- int i, rc = 0;
- char *src_ptr, *dst_ptr;
-
- src_ptr = (char *)src;
- dst_ptr = (char *)addr;
- pages = cnt / PAGE_SIZE;
- remain = cnt % PAGE_SIZE;
- if (pages) {
- for (i = 0; i < pages; i++) {
- if ((i % 500) == 0)
- putc('.');
- buffered_wirte_nor_flash((u32) dst_ptr, (u8 *) src_ptr,
- (u16) PAGE_SIZE);
- if ((rc = flash_full_status_check((u32) dst_ptr)) != 0)
- break;
- dst_ptr += PAGE_SIZE;
- src_ptr += PAGE_SIZE;
- }
- }
-
- if (remain) {
- buffered_wirte_nor_flash((u32) dst_ptr, (u8 *) src_ptr,
- (u16) remain);
- rc = flash_full_status_check((u32) dst_ptr);
- }
-
- printf("\nCopied 0x%x bytes from 0x%x to 0x%x\r\n", cnt, src, addr);
- return rc;
-
-#else
- u32 *sp, *dp;
- char *src_ptr, *dst_ptr;
- u32 len, remain, i;
- int rc = 0;
- sp = (u32 *) src;
- dp = (u32 *) addr;
- len = cnt & ~0x3;
- remain = cnt % 4;
-
- while (len) {
- if ((len % 2000) == 0)
- putc('.');
- if ((rc = write_word(info, dp, *sp)) != 0)
- break;
- dp++;
- sp++;
- len -= 4;
- }
- src_ptr = (char *)sp;
- dst_ptr = (char *)dp;
- if (remain) {
- for (i = 0; i < remain; i++) {
- write_byte_nor_flash((dst_ptr + i), *(src_ptr + i));
- }
- rc = flash_full_status_check((u32) dst_ptr);
- }
- printf("\nCopied 0x%xbytes from 0x%x to 0x%x\r\n", cnt, src, addr);
- return rc;
-
-#endif
-}
-
-#endif
+++ /dev/null
-
-/******************************************************************************
-*
-* $xilinx_legal_disclaimer
-*
-******************************************************************************/
-
-#include "pl353_x8.h"
-/*
- * init_nor_flash init the parameters of pl353 for the P30 flash
- */
-//typedef volatile u32 XIo_Address;
-
-void Xil_Out8(XIo_Address OutAddress, u8 Value);
-u8 Xil_In8(XIo_Address InAddress);
-
-void init_nor_flash(void)
-{
- /* Init variables */
-
- /* Write timing info to set_cycles registers */
- u32 set_cycles_reg = (0x0 << 20) | /* Set_t6 or we_time from sram_cycles */
- (0x0 << 17) | /* Set_t5 or t_tr from sram_cycles */
- (0x1 << 14) | /* Set_t4 or t_pc from sram_cycles */
- (0x5 << 11) | /* Set_t3 or t_wp from sram_cycles */
- (0x1 << 8) | /* Set_t2 t_ceoe from sram_cycles */
- (0x7 << 4) | /* Set_t1 t_wc from sram_cycles */
- (0x7); /* Set_t0 t_rc from sram_cycles */
-
- X_mWriteReg(PARPORT_CRTL_BASEADDR, PARPORT_MC_SET_CYCLES, set_cycles_reg);
-
- /* write operation mode to set_opmode registers */
- u32 set_opmode_reg = (0x1 << 13) | /* set_burst_align, see to 32 beats */
- (0x0 << 12) | /* set_bls, set to default I am not sure */
- (0x0 << 11) | /* set_adv bit, set to default */
- (0x0 << 10) | /* set_baa, I guess we don't use baa_n */
- (0x0 << 7) | /* set_wr_bl, write brust length, set to 0 */
- (0x0 << 6) | /* set_wr_sync, set to 0 */
- (0x0 << 3) | /* set_rd_bl, read brust lenght, set to 0 */
- (0x0 << 2) | /* set_rd_sync, set to 0 */
- (0x0 ); /* set_mw, memory width, 16bits width*/
- X_mWriteReg(PARPORT_CRTL_BASEADDR, PARPORT_MC_SET_OPMODE, set_opmode_reg);
-
-
- /*
- * Issue a direct_cmd by writing to direct_cmd register
- * This is needed becuase the UpdatesReg flag in direct_cmd updates the state of SMC
- * I think....
- */
- u32 direct_cmd_reg = (0x0 << 23) | /* chip 0 from interface 0 */
- (0x2 << 21) | /* UpdateRegs operation, to update the two reg we wrote earlier*/
- (0x0 << 20) | /* Not sure about this one cre, what does it do? */
- (0x0); /* addr, not use in UpdateRegs */
- X_mWriteReg(PARPORT_CRTL_BASEADDR, PARPORT_MC_DIRECT_CMD, direct_cmd_reg);
-
- /* Now the flash should be ready to be accessed */
-}
-
-
-/*
- * wirte_nor_flash returns 1 after a seccussful write
- */
-void write_half_word_nor_flash(u32 address, u8 data)
-{
- /* status reg polling to be added later */
- Xil_Out8(address, 0x40);
- Xil_Out8(address, data);
- while(read_status_reg_nor_flash(address) >> 7 != 1);
-}
-
-void write_byte_nor_flash(u32 address, u8 data)
-{
- Xil_Out8(address, 0x40);
- Xil_Out8(address, data);
- while(read_status_reg_nor_flash(address) >> 7 != 1);
-}
-/*
- * read_nor_flash returns the data of a memeory location
- */
-u16 read_half_word_nor_flash(u32 address)
-{
- Xil_Out8(address, 0xFF);
- return Xil_In8(address);
-}
-
-/*
- * read_status_reg_nor_flash returns the status register of a block address
- */
-u16 read_status_reg_nor_flash(u32 address)
-{
- Xil_Out8(address, 0x70);
- return Xil_In8(address);
-}
-
-/*
- * clear_status_reg_nor_flash clears the status register of a block address
- */
-void clear_status_reg_nor_flash(u32 address)
-{
- Xil_Out8(address, 0x50);
-}
-
-/*
- * unlock_nor_flash put the selected block of address in unlock mode
- */
-void unlock_nor_flash(u32 blockAddress)
-{
- Xil_Out8((blockAddress & 0xFFFF0000), 0x60);
- Xil_Out8((blockAddress & 0xFFFF0000), 0xD0);
-}
-
-/*
- * lock_nor_flash put the selected block of address in lock mode
- */
-void lock_nor_flash(u32 blockAddress)
-{
- Xil_Out8((blockAddress & 0xFFFF0000), 0x60);
- Xil_Out8((blockAddress & 0xFFFF0000), 0x01);
-}
-
-/*
- * block_erase_nor_flash
- */
-void block_erase_nor_flash(u32 blockAddress)
-{
- /* Clear status before erase */
- if(read_status_reg_nor_flash(blockAddress & 0xFFFF0000) != 0x80)
- {
- clear_status_reg_nor_flash(blockAddress & 0xFFFF0000);
- }
-
- Xil_Out8((blockAddress & 0xFFFF0000), 0x20);
- Xil_Out8((blockAddress & 0xFFFF0000), 0xD0);
-
- while(Xil_In8((blockAddress & 0xFFFF0000)) >> 7 != 1);
-
-}
-
-/*
- * buffered_write_nor_flash
- */
-void buffered_wirte_nor_flash(u32 address, u8 *dataBuffer, u16 wordCount)
-{
-
- /* Issue write program */
- Xil_Out8((address & 0xFFFF0000), 0xE8);
-
- /* Poll status reg at block address until ready*/
- while(Xil_In8((address & 0xFFFF0000)) >> 7 != 1);
-
- /* write count to block address */
- Xil_Out8((address & 0xFFFF0000), wordCount - 1);
-
- /* write data */
- int i;
- for(i = 0; i < wordCount; i++)
- {
- Xil_Out8((address + i), dataBuffer[i]);
- }
-
- /* write confirm to block address */
- Xil_Out8((address & 0xFFFF0000), 0xD0);
-
- /* Poll status reg */
- while(Xil_In8((address & 0xFFFF0000)) >> 7 != 1);
-
-
-}
-void Xil_Out8(XIo_Address OutAddress, u8 Value)
-{
- *(volatile u8 *) OutAddress = Value;
-}
-
-u8 Xil_In8(XIo_Address InAddress)
-{
- return *(u8 *) InAddress;
-}
+++ /dev/null
- /******************************************************************************
-*
-* $xilinx_legal_disclaimer
-*
-******************************************************************************/
-
-#ifndef pl353_H
-#define pl353_H
-
-#include <common.h>
-/* pl353 base address*/
-#define PARPORT_CRTL_BASEADDR 0xE000E000
-#define NOR_FLASH_BASEADDR 0xE2000000
-
-/* Now for the register offsets */
-#define PARPORT_MC_OFFSET 0x000 /* Begining of Memory controller config reg offset */
-
-#define PARPORT_MC_STATUS 0x000
-#define PARPORT_MC_INTERFACE_CONFIG 0x004
-#define PARPORT_MC_SET_CONFIG 0x008
-#define PARPORT_MC_CLR_CONFIG 0x00C
-#define PARPORT_MC_DIRECT_CMD 0x010
-#define PARPORT_MC_SET_CYCLES 0x014
-#define PARPORT_MC_SET_OPMODE 0x018
-#define PARPORT_MC_REFRESH_PERIOD_0 0x020
-#define PARPORT_MC_REFRESH_PERIOD_1 0x024
-
-#define PARPORT_CS_OFFSET 0x100 /* Begining of Chip select config reg offset*/
-
-#define PARPORT_CS_INTERFACE_1_CHIP_3_OFFSET 0x1E0 /* Interface 1 chip 3 configuration */
-#define PARPORT_CS_INTERFACE_1_CHIP_2_OFFSET 0x1C0 /* Interface 1 chip 2 configuration */
-#define PARPORT_CS_INTERFACE_1_CHIP_1_OFFSET 0x1A0 /* Interface 1 chip 1 configuration */
-#define PARPORT_CS_INTERFACE_1_CHIP_0_OFFSET 0x180 /* Interface 1 chip 0 configuration */
-#define PARPORT_CS_INTERFACE_0_CHIP_3_OFFSET 0x160 /* Interface 0 chip 3 configuration */
-#define PARPORT_CS_INTERFACE_0_CHIP_2_OFFSET 0x140 /* Interface 0 chip 2 configuration */
-#define PARPORT_CS_INTERFACE_0_CHIP_1_OFFSET 0x120 /* Interface 0 chip 1 configuration */
-#define PARPORT_CS_INTERFACE_0_CHIP_0_OFFSET 0x100 /* Interface 0 chip 0 configuration */
-
-#define PARPORT_UC_OFFSET 0x200 /* Begining of User config reg offset*/
-
-#define PARPORT_UC_CONFIG_OFFSET 0x204 /* user config reg */
-#define PARPORT_UC_STATUS_OFFSET 0x200 /* user status reg */
-
-#define PARPORT_IT_OFFSET 0xE00 /* Inegration test */
-
-#define PARPORT_ID_OFFSET 0xFE0 /* Begining of PrimeCell ID config reg offset*/
-#define PARPORT_ID_PCELL_3_OFFSET 0xFFC
-#define PARPORT_ID_PCELL_2_OFFSET 0xFF8
-#define PARPORT_ID_PCELL_1_OFFSET 0xFF4
-#define PARPORT_ID_PCELL_0_OFFSET 0xFF0
-#define PARPORT_ID_PERIP_3_OFFSET 0xFEC
-#define PARPORT_ID_PERIP_2_OFFSET 0xFE8
-#define PARPORT_ID_PERIP_1_OFFSET 0xFE4
-#define PARPORT_ID_PERIP_0_OFFSET 0xFE0
-
-/* Read Write macros */
-
-/* Write to memory location or register */
-#define X_mWriteReg(BASE_ADDRESS, RegOffset, data) \
- *(unsigned long *)(BASE_ADDRESS + RegOffset) = ((unsigned long) data);
-/* Read from memory location or register */
-#define X_mReadReg(BASE_ADDRESS, RegOffset) \
- *(unsigned long *)(BASE_ADDRESS + RegOffset);
-
-typedef volatile u32 XIo_Address;
-
-typedef u32 AddressType;
-
-void Xil_Out8(XIo_Address OutAddress, u8 Value);
-u8 Xil_In8(XIo_Address InAddress);
-
-/* Function definitionas */
-/*
- * init_nor_flash init the parameters of pl353 for the P30 flash
- */
-void init_nor_flash(void);
-
-/*
- * wirte_nor_flash
- */
-void write_half_word_nor_flash(u32 address, u8 data);
-void write_byte_nor_flash(u32 address, u8 data);
-/*
- * read_nor_flash returns the data of a memeory location
- */
-u16 read_half_word_nor_flash(u32 address);
-
-/*
- * read_status_reg_nor_flash returns the status register of a block address
- */
-u16 read_status_reg_nor_flash(u32 address);
-
-/*
- * clear_status_reg_nor_flash clears the status register of a block address
- */
-void clear_status_reg_nor_flash(u32 address);
-
-/*
- * unlock_nor_flash put the selected block of address in unlock mode
- */
-void unlock_nor_flash(u32 blockAddress);
-
-/*
- * lock_nor_flash put the selected block of address in lock mode
- */
-void lock_nor_flash(u32 blockAddress);
-
-/*
- * block_erase_nor_flash
- */
-void block_erase_nor_flash(u32 blockAddress);
-
-/*
- * bufferred_write_nor_flash
- */
-void buffered_wirte_nor_flash(u32 address, u8 *dataBuffer, u16 wordCount);
-
-#endif
/* PSS Interrupt controller defines */
#define XPAR_GIC_SINGLE_DEVICE_ID 0
-#define XPAR_GIC_CPU_BASEADDR XPAR_SCUGIC_CPU_BASEADDR
-#define XPAR_GIC_DIST_BASEADDR XPAR_SCUGIC_DIST_BASEADDR
+#define XPAR_GIC_CPU_BASEADDR XPSS_GIC_CPU_BASEADDR
+#define XPAR_GIC_DIST_BASEADDR XPSS_GIC_DIS_BASEADDR
#define XPAR_GIC_NUM_INSTANCES 1
#define XPAR_GIC_ACK_BEFORE 0
/* UART Defines */
-#define XPAR_XUARTPSS_NUM_INSTANCES 2
#define XPAR_XUARTPSS_0_DEVICE_ID 0
#define XPAR_XUARTPSS_0_BASEADDR XPSS_UART0_BASEADDR
#define XPAR_XUARTPSS_0_CLOCK_HZ 50000000
-#define XPAR_XUARTPSS_0_INTR XPSS_UART0_INT_ID
+#define XPAR_XUARTPSS_0_INTR 51
#define XPAR_XUARTPSS_1_DEVICE_ID 1
#define XPAR_XUARTPSS_1_BASEADDR XPSS_UART1_BASEADDR
#define XPAR_XUARTPSS_1_CLOCK_HZ 50000000
-#define XPAR_XUARTPSS_1_INTR XPSS_UART1_INT_ID
+#define XPAR_XUARTPSS_1_INTR 75
+#define XPAR_XUARTPSS_NUM_INSTANCES 2
/*IIC Defines */
#define XPAR_XIICPSS_NUM_INSTANCES 2
-#define XPAR_XIICPSS_0_DEVICE_ID 0
-#define XPAR_XIICPSS_0_BASEADDR XPSS_I2C0_BASEADDR
+#define XPAR_XIICPSS_0_DEVICE_ID 0 /* Device ID for instance */
+#define XPAR_XIICPSS_0_BASEADDR XPSS_I2C0_BASEADDR /* Device base address */
#define XPAR_XIICPSS_0_CLOCK_HZ 100000000
-#define XPAR_XIICPSS_0_INTR XPSS_I2C0_INT_ID
-#define XPAR_XIICPSS_1_DEVICE_ID 1
-#define XPAR_XIICPSS_1_BASEADDR XPSS_I2C1_BASEADDR
+#define XPAR_XIICPSS_0_INTR 48
+#define XPAR_XIICPSS_1_DEVICE_ID 1 /* Device ID for instance */
+#define XPAR_XIICPSS_1_BASEADDR XPSS_I2C1_BASEADDR /* Device base address */
#define XPAR_XIICPSS_1_CLOCK_HZ 100000000
-#define XPAR_XIICPSS_1_INTR XPSS_I2C1_INT_ID
-
-/* SPI Defines */
-#define XPAR_XSPIPSS_NUM_INSTANCES 2
-#define XPAR_XSPIPSS_0_DEVICE_ID 0
-#define XPAR_XSPIPSS_0_BASEADDR XPSS_SPI0_BASEADDR
-#define XPAR_XSPIPSS_0_CLOCK_HZ 50000000
-#define XPAR_XSPIPSS_0_INTR XPSS_SPI0_INT_ID
-#define XPAR_XSPIPSS_1_DEVICE_ID 1
-#define XPAR_XSPIPSS_1_BASEADDR XPSS_SPI1_BASEADDR
-#define XPAR_XSPIPSS_1_CLOCK_HZ 50000000
-#define XPAR_XSPIPSS_1_INTR XPSS_SPI1_INT_ID
-
-/* CAN Defines */
-#define XPAR_XCANPSS_NUM_INSTANCES 1
-#define XPAR_XCANPSS_0_DEVICE_ID 0
-#define XPAR_XCANPSS_0_BASEADDR XPSS_CAN0_BASEADDR
-#define XPAR_XCANPSS_0_INTR XPSS_CAN0_INT_ID
-
-/* DMA Defines */
-#define XPAR_XDMAPSS_NUM_INSTANCES 1
-#define XPAR_XDMAPSS_0_DEVICE_ID 0
-#define XPAR_XDMAPSS_0_BASEADDR XPSS_DMAC0_BASEADDR
-#define XPAR_XDMAPSS_0_FAULT_INTR XPSS_TOP_DMA_ABORT_INT_ID
-#define XPAR_XDMAPSS_0_DONE_INTR_0 XPSS_TOP_DMA0_INT_ID
-#define XPAR_XDMAPSS_0_DONE_INTR_1 XPSS_TOP_DMA1_INT_ID
-#define XPAR_XDMAPSS_0_DONE_INTR_2 XPSS_TOP_DMA2_INT_ID
-#define XPAR_XDMAPSS_0_DONE_INTR_3 XPSS_TOP_DMA3_INT_ID
-#define XPAR_XDMAPSS_0_DONE_INTR_4 XPSS_BOT_DMA0_INT_ID
-#define XPAR_XDMAPSS_0_DONE_INTR_5 XPSS_BOT_DMA1_INT_ID
-#define XPAR_XDMAPSS_0_DONE_INTR_6 XPSS_BOT_DMA2_INT_ID
-#define XPAR_XDMAPSS_0_DONE_INTR_7 XPSS_BOT_DMA3_INT_ID
-
-#define XPAR_XDMAPSS_CHANNELS_PER_DEV 4
-
-/* GPIO Defines*/
-#define XPAR_XGPIO_NUM_INSTANCES 1
-#define XPAR_XGPIO_0_DEVICE_ID 0
-#define XPAR_XGPIO_0_BASEADDR XPSS_GPIO_BASEADDR
-#define XPAR_XGPIO_0_INTR XPSS_GPIO_INT_ID
-
-/* GEM Defines*/
-#define XPAR_XEMACPSS_NUM_INSTANCES 1
-#define XPAR_XEMACPSS_0_DEVICE_ID 0
-#define XPAR_XEMACPSS_0_BASEADDR XPSS_GEM0_BASEADDR
-#define XPAR_XEMACPSS_0_INTR XPSS_GEM0_INT_ID
-#define XPAR_XEMACPSS_1_DEVICE_ID 1
-#define XPAR_XEMACPSS_1_BASEADDR XPSS_GEM1_BASEADDR
+#define XPAR_XIICPSS_1_INTR 73
/* TTC Defines */
#define XPAR_XTTCPSS_NUM_INSTANCES 6
#define XPAR_XTTCPSS_CLOCK_HZ 781250
#define XPAR_XTTCPSS_0_DEVICE_ID 0
-#define XPAR_XTTCPSS_0_BASEADDR XPSS_TTC0_BASEADDR
+#define XPAR_XTTCPSS_0_BASEADDR XPSS_TTC0_BASEADDR /* Device base address */
#define XPAR_XTTCPSS_0_INTR XPSS_TTC0_0_INT_ID
#define XPAR_XTTCPSS_0_CLOCK_HZ XPAR_XTTCPSS_CLOCK_HZ
#define XPAR_XTTCPSS_1_DEVICE_ID 1
-#define XPAR_XTTCPSS_1_BASEADDR XPSS_TTC0_BASEADDR+4
+#define XPAR_XTTCPSS_1_BASEADDR XPSS_TTC0_BASEADDR+4 /* Device base address */
#define XPAR_XTTCPSS_1_CLOCK_HZ XPAR_XTTCPSS_CLOCK_HZ
#define XPAR_XTTCPSS_1_INTR XPSS_TTC0_1_INT_ID
#define XPAR_XTTCPSS_2_DEVICE_ID 2
-#define XPAR_XTTCPSS_2_BASEADDR XPSS_TTC0_BASEADDR+8
+#define XPAR_XTTCPSS_2_BASEADDR XPSS_TTC0_BASEADDR+8 /* Device base address */
#define XPAR_XTTCPSS_2_CLOCK_HZ XPAR_XTTCPSS_CLOCK_HZ
#define XPAR_XTTCPSS_2_INTR XPSS_TTC0_2_INT_ID
#define XPAR_XTTCPSS_3_DEVICE_ID 3
-#define XPAR_XTTCPSS_3_BASEADDR XPSS_TTC1_BASEADDR
+#define XPAR_XTTCPSS_3_BASEADDR XPSS_TTC1_BASEADDR /* Device base address */
#define XPAR_XTTCPSS_3_INTR XPSS_TTC1_0_INT_ID
#define XPAR_XTTCPSS_3_CLOCK_HZ XPAR_XTTCPSS_CLOCK_HZ
#define XPAR_XTTCPSS_4_DEVICE_ID 4
-#define XPAR_XTTCPSS_4_BASEADDR XPSS_TTC1_BASEADDR+4
+#define XPAR_XTTCPSS_4_BASEADDR XPSS_TTC1_BASEADDR+4 /* Device base address */
#define XPAR_XTTCPSS_4_CLOCK_HZ XPAR_XTTCPSS_CLOCK_HZ
#define XPAR_XTTCPSS_4_INTR XPSS_TTC1_1_INT_ID
#define XPAR_XTTCPSS_5_DEVICE_ID 5
-#define XPAR_XTTCPSS_5_BASEADDR XPSS_TTC1_BASEADDR+8
+#define XPAR_XTTCPSS_5_BASEADDR XPSS_TTC1_BASEADDR+8 /* Device base address */
#define XPAR_XTTCPSS_5_CLOCK_HZ XPAR_XTTCPSS_CLOCK_HZ
#define XPAR_XTTCPSS_5_INTR XPSS_TTC1_2_INT_ID
+/* GPIO Defines*/
+#define XPAR_XGPIO_NUM_INSTANCES 1
+#define XPAR_XGPIO_0_DEVICE_ID 0
+#define XPAR_XGPIO_BASEADDR XPSS_GPIO_BASEADDR
+
+/* GEM Defines*/
+#define XPAR_XEMACPSS_NUM_INSTANCES 2
+#define XPAR_XEMACPSS_0_DEVICE_ID 0
+#define XPAR_XEMACPSS_0_BASEADDR XPSS_GEM0_BASEADDR
+#define XPAR_XEMACPSS_1_DEVICE_ID 1
+#define XPAR_XEMACPSS_1_BASEADDR XPSS_GEM1_BASEADDR
+
+/* SPI Defines */
+#define XPAR_XSPIPSS_NUM_INSTANCES 2
+#define XPAR_SPIPSS_0_DEVICE_ID 0 /* Device ID for instance */
+#define XPAR_SPIPSS_0_BASEADDR XPSS_SPI0_BASEADDR
+#define XPAR_SPIPSS_0_CLOCK_HZ 50000000
+
+#define XPAR_SPIPSS_1_DEVICE_ID 1 /* Device ID for instance */
+#define XPAR_SPIPSS_1_BASEADDR XPSS_SPI1_BASEADDR
+#define XPAR_SPIPSS_1_CLOCK_HZ 50000000
+#define XPAR_SPIPSS_1_INTR 7
+
/* WDT Defines*/
#define XPSS_WDT_NUM_INSTANCES 1
#define XPSS_WDT_DEVICE_ID 0
-/* $Id: xparameters_pss.h,v 1.1.2.1 2010/01/07 06:11:50 sadanan Exp $ */
+/* $Id: xparameters_pss.h,v 1.1.2.3 2009/07/01 21:42:22 meinelte Exp $ */
/******************************************************************************
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
* @file xparameters_pss.h
*
* This file contains the address definitions for the hard peripherals
-* attached to the ARM11 core.
+* attached to the Cortex A9 core.
*
* <pre>
* MODIFICATION HISTORY:
* 1.00a ecm 02/01/09 Initial version,
* </pre>
*
-* @note
-*
-* None.
+* @note None.
*
******************************************************************************/
/************************** Constant Definitions *****************************/
+#define RTL_20 /* Palladium now */
+
/*
* This block contains constant declarations for the peripherals
* within the hardblock
*/
-
#define XPSS_PERIPHERAL_BASEADDR 0xE0000000
#define XPSS_UART0_BASEADDR 0xE0000000
#define XPSS_UART1_BASEADDR 0xE0001000
+
+
#define XPSS_USB0_BASEADDR 0xE0002000
#define XPSS_USB1_BASEADDR 0xE0003000
#define XPSS_I2C0_BASEADDR 0xE0004000
#define XPSS_USB0_SLAVE_BASEADDR 0xE0100000
#define XPSS_USB1_SLAVE_BASEADDR 0xE0110000
+
+#define XPSS_SDIO0_BASEADDR 0xE0100000
+#define XPSS_SDIO1_BASEADDR 0xE0101000
+
+#define XPSS_IOU_BUS_CFG_BASEADDR 0xE0200000
+
+#define XPSS_NAND_BASEADDR 0xE1000000
+
#define XPSS_PARPORT0_BASEADDR 0xE2000000
#define XPSS_PARPORT1_BASEADDR 0xE4000000
+#ifdef RTL_30
+#define XPSS_QSPI_LIN_BASEADDR 0xFC000000
-#define XPSS_NAND_BASEADDR 0xE1000000
+#define XPSS_SYS_CTRL_BASEADDR 0xF8000000 /* AKA SLCR */
-#define XPSS_GIC_CPU_BASEADDR 0xE8000000
+#define XPSS_TTC0_BASEADDR 0xF8001000
+#define XPSS_TTC1_BASEADDR 0xF8002000
-#define XPSS_SAM_CTRL_BASEADDR 0xE9000000
+#define XPSS_DMAC0_BASEADDR 0xF8003000
+#define XPSS_DMAC1_BASEADDR 0xF8004000
-#define XPSS_DEV_CFG_AXI_BASEADDR 0xEA000000
+#define XPSS_WDT_BASEADDR 0xF8005000
+#define XPSS_DDR_CTRL_BASEADDR 0xF8006000
-#define XPSS_DMAC0_BASEADDR 0xEC000000
-#define XPSS_DMAC1_BASEADDR 0xEC001000
+#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
-#define XPSS_WDT_BASEADDR 0xEC002000
-#define XPSS_DDR_CTRL_BASEADDR 0xEC003000
+#define XPSS_L2CC_BASEADDR 0xF8F02000
-#define XPSS_DEV_CFG_APB_BASEADDR 0xEA005000
-#define XPSS_L2CC_BASEADDR 0xFDF00000
+#define XPSS_SCU_BASEADDR 0xF8F00000
-#define XPSS_SYS_CTRL_BASEADDR 0x90000000 /* AKA SLCR */
+#else
-/* vijc
- * #define XPSS_TTC0_BASEADDR 0xFE001000
- *#define XPSS_TTC1_BASEADDR 0xFE002000
- */
+#define XPSS_QSPI_LIN_BASEADDR 0xE6000000
- #define XPSS_TTC0_BASEADDR 0x90001000
- #define XPSS_TTC1_BASEADDR 0x90002000
+#define XPSS_SYS_CTRL_BASEADDR 0xFE000000 /* AKA SLCR */
-#define XPSS_CORE_SWITCH_BASEADDR 0x90003000
-#define XPSS_DMA_SWITCH_BASEADDR 0x90004000
-#define XPSS_IOU_M_SWITCH_BASEADDR 0x90005000
-#define XPSS_IOU_S_SWITCH_BASEADDR 0x90006000
-#define XPSS_FPGA_M_SWITCH_BASEADDR 0x90007000
-#define XPSS_FPGA_S_SWITCH_BASEADDR 0x90008000
+#define XPSS_TTC0_BASEADDR 0xFE001000
+#define XPSS_TTC1_BASEADDR 0xFE002000
-#define XPSS_GIC_DIS_BASEADDR 0x90100000
+#define XPSS_DMAC0_BASEADDR 0xFE003000
+#define XPSS_DMAC1_BASEADDR 0xFE004000
-#define XPSS_SAM_RAM_BASEADDR 0xFFFC0000
+#define XPSS_WDT_BASEADDR 0xFE005000
+#define XPSS_DDR_CTRL_BASEADDR 0xFE006000
+#define XPSS_DEV_CFG_APB_BASEADDR 0xFE007000
-/* Interrupt Controller bit assignments */
+#define XPSS_L2CC_BASEADDR 0xFFE00000
-/* Shared Peripheral Interrupts (SPI) */
-#define XPSS_WDT_INT_ID 32
-#define XPSS_TTC0_0_INT_ID 33
-#define XPSS_TTC0_1_INT_ID 34
-#define XPSS_TTC0_2_INT_ID 35
-#define XPSS_TOP_DMA_ABORT_INT_ID 36
-#define XPSS_TOP_DMA0_INT_ID 37
-#define XPSS_TOP_DMA1_INT_ID 38
-#define XPSS_TOP_DMA2_INT_ID 39
-#define XPSS_TOP_DMA3_INT_ID 40
-#define XPSS_SAM_SEC_INT_ID 41
-#define XPSS_SMC_INT_ID 42
-#define XPSS_QSPI_INT_ID 43
-#define XPSS_CTI_INT_ID 44
-#define XPSS_GPIO_INT_ID 45
-#define XPSS_USB0_INT_ID 46
-#define XPSS_GEM0_INT_ID 47
-#define XPSS_GEM0_WAKE_INT_ID 48
-#define XPSS_SDIO0_INT_ID 49
-#define XPSS_I2C0_INT_ID 50
-#define XPSS_SPI0_INT_ID 51
-#define XPSS_UART0_INT_ID 52
-#define XPSS_CAN0_INT_ID 53
-#define XPSS_FPGA0_INT_ID 54
-#define XPSS_FPGA1_INT_ID 55
-#define XPSS_FPGA2_INT_ID 56
-#define XPSS_FPGA3_INT_ID 57
-#define XPSS_FPGA4_INT_ID 58
-#define XPSS_FPGA5_INT_ID 59
-#define XPSS_FPGA6_INT_ID 60
-#define XPSS_FPGA7_INT_ID 61
-#define XPSS_TTC1_0_INT_ID 62
-#define XPSS_TTC1_1_INT_ID 63
-#define XPSS_TTC1_2_INT_ID 64
-#define XPSS_BOT_DMA_ABOR_INT_ID 65
-#define XPSS_BOT_DMA0_INT_ID 66
-#define XPSS_BOT_DMA1_INT_ID 67
-#define XPSS_BOT_DMA2_INT_ID 68
-#define XPSS_BOT_DMA3_INT_ID 69
-#define XPSS_SAM_NOSEC_INT_ID 70
-#define XPSS_USB1_INT_ID 71
-#define XPSS_GEM1_INT_ID 72
-#define XPSS_GEM1_WAKE_INT_ID 73
-#define XPSS_SDIO1_INT_ID 74
-#define XPSS_I2C1_INT_ID 75
-#define XPSS_SPI1_INT_ID 76
-#define XPSS_UART1_INT_ID 77
-#define XPSS_CAN1_INT_ID 78
-#define XPSS_FPGA8_INT_ID 79
-
-#define XPSS_FPGA9_INT_ID 80
-#define XPSS_FPGA10_INT_ID 81
-#define XPSS_FPGA11_INT_ID 82
-#define XPSS_FPGA12_INT_ID 83
-#define XPSS_FPGA13_INT_ID 84
-#define XPSS_FPGA14_INT_ID 85
-#define XPSS_FPGA15_INT_ID 86
+#define XPSS_SCU_BASEADDR 0xFEF00000
-/* Private Peripheral Interrupts (PPI) */
+#endif
-#define XPSS_CPU_NDMAS_INT_ID 16 /* ARM1176 Internal DMA interrupt */
-#define XPSS_CPU_NDMA_INT_ID 17 /* ARM1176 Internal DMA interrupt */
-#define XPSS_CPU_NDMAEXTERR_INT_ID 18 /* ARM1176 Internal DMA interrupt */
-#define XPSS_NPMU_INT_ID 19 /* ARM1176 Internal system metric block */
-#define XPSS_NVALF_INT_ID 20 /* ARM1176 validation FIQ */
-#define XPSS_NVALI_INT_ID 21 /* ARM1176 validation IRQ */
-#define XPSS_L2CCINTR_INT_ID 22 /* ARM1176 L2 IRQ */
-#define XPSS_DEV_SEC_INT_ID 23 /* Device security interrupt */
+/* Interrupt Controller bit assignments */
+/* Shared Peripheral Interrupts (SPI) */
+#define XPSS_L2CC_INT_ID 32
+#define XPSS_DEV_CFG_INT_ID 33
+#define XPSS_WDT_INT_ID 34
+#define XPSS_TTC0_0_INT_ID 35
+#define XPSS_TTC0_1_INT_ID 36
+#define XPSS_TTC0_2_INT_ID 37
+#define XPSS_TOP_DMA_ABORT_INT_ID 38
+#define XPSS_TOP_DMA0_INT_ID 39
+#define XPSS_TOP_DMA1_INT_ID 40
+#define XPSS_TOP_DMA2_INT_ID 41
+#define XPSS_TOP_DMA3_INT_ID 42
+//#define XPSS_SAM_SEC_INT_ID 41
+#define XPSS_SMC_INT_ID 43
+#define XPSS_QSPI_INT_ID 44
+//#define XPSS_CTI_INT_ID 44
+#define XPSS_GPIO_INT_ID 45
+#define XPSS_USB0_INT_ID 46
+#define XPSS_GEM0_INT_ID 47
+#define XPSS_GEM0_WAKE_INT_ID 48
+#define XPSS_SDIO0_INT_ID 49
+#define XPSS_I2C0_INT_ID 50
+#define XPSS_SPI0_INT_ID 51
+#define XPSS_UART0_INT_ID 52
+#define XPSS_CAN0_INT_ID 53
+#define XPSS_FPGA0_INT_ID 54
+#define XPSS_FPGA1_INT_ID 55
+#define XPSS_FPGA2_INT_ID 56
+#define XPSS_FPGA3_INT_ID 57
+#define XPSS_FPGA4_INT_ID 58
+#define XPSS_FPGA5_INT_ID 59
+#define XPSS_FPGA6_INT_ID 60
+#define XPSS_FPGA7_INT_ID 61
+#define XPSS_TTC1_0_INT_ID 62
+#define XPSS_TTC1_1_INT_ID 63
+#define XPSS_TTC1_2_INT_ID 64
+//#define XPSS_BOT_DMA_ABOR_INT_ID 65
+#define XPSS_BOT_DMA0_INT_ID 65
+#define XPSS_BOT_DMA1_INT_ID 66
+#define XPSS_BOT_DMA2_INT_ID 67
+#define XPSS_BOT_DMA3_INT_ID 68
+//#define XPSS_SAM_NOSEC_INT_ID 70
+#define XPSS_USB1_INT_ID 69
+#define XPSS_GEM1_INT_ID 70
+#define XPSS_GEM1_WAKE_INT_ID 71
+#define XPSS_SDIO1_INT_ID 72
+#define XPSS_I2C1_INT_ID 73
+#define XPSS_SPI1_INT_ID 74
+#define XPSS_UART1_INT_ID 75
+#define XPSS_CAN1_INT_ID 76
+#define XPSS_FPGA8_INT_ID 77
+#define XPSS_FPGA9_INT_ID 78
+#define XPSS_FPGA10_INT_ID 79
+#define XPSS_FPGA11_INT_ID 80
+#define XPSS_FPGA12_INT_ID 81
+#define XPSS_FPGA13_INT_ID 82
+#define XPSS_FPGA14_INT_ID 83
+#define XPSS_FPGA15_INT_ID 84
+/* Private Peripheral Interrupts (PPI) */
+#define XPSS_GLOBAL_TMR_INT_ID 27
+#define XPSS_CPU_TMR_INT_ID 29
+#define XPSS_SCU_WDT_INT_ID 30
/* L2CC Register Offsets */
-#define XPSS_L2CC_ID_OFFSET 0x0000
-#define XPSS_L2CC_TYPE_OFFSET 0x0004
-#define XPSS_L2CC_CNTRL_OFFSET 0x0100
-#define XPSS_L2CC_AUX_CNTRL_OFFSET 0x0104
+#define XPSS_L2CC_ID_OFFSET 0x0000
+#define XPSS_L2CC_TYPE_OFFSET 0x0004
+#define XPSS_L2CC_CNTRL_OFFSET 0x0100
+#define XPSS_L2CC_AUX_CNTRL_OFFSET 0x0104
#define XPSS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108
#define XPSS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010C
-#define XPSS_L2CC_EVNT_CNTRL_OFFSET 0x0200
+#define XPSS_L2CC_EVNT_CNTRL_OFFSET 0x0200
#define XPSS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204
#define XPSS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208
#define XPSS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020C
#define XPSS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210
-#define XPSS_L2CC_IER_OFFSET 0x0214 /* Interrupt Mask */
-#define XPSS_L2CC_IPR_OFFSET 0x0218 /* Masked interrupt status */
-#define XPSS_L2CC_ISR_OFFSET 0x021C /* Raw Interrupt Status */
-#define XPSS_L2CC_IAR_OFFSET 0x0220 /* Interrupt Clear */
-
-#define XPSS_L2CC_CACHE_SYNC_OFFSET 0x0730 /* Cache Sync */
-#define XPSS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770 /* Cache Invalid by PA */
-#define XPSS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077C /* Cache Invalid by Way */
-#define XPSS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0 /* Cache Clean by PA */
-#define XPSS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8 /* Cache Clean by Index */
-#define XPSS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BC /* Cache Clean by Way */
-#define XPSS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0 /* Cache Invalidate and Clean by PA */
-#define XPSS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8 /* Cache Invalidate and Clean by Index */
-#define XPSS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FC /* Cache Invalidate and Clean by Way */
-
-
-#define XPSS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900 /* Cache Data Lockdown 0 by Way */
-#define XPSS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904 /* Cache Instruction Lockdown 0 by Way */
-#define XPSS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908 /* Cache Data Lockdown 1 by Way */
-#define XPSS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090C /* Cache Instruction Lockdown 1 by Way */
-#define XPSS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910 /* Cache Data Lockdown 2 by Way */
-#define XPSS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914 /* Cache Instruction Lockdown 2 by Way */
-#define XPSS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918 /* Cache Data Lockdown 3 by Way */
-#define XPSS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091C /* Cache Instruction Lockdown 3 by Way */
-#define XPSS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920 /* Cache Data Lockdown 4 by Way */
-#define XPSS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924 /* Cache Instruction Lockdown 4 by Way */
-#define XPSS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928 /* Cache Data Lockdown 5 by Way */
-#define XPSS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092C /* Cache Instruction Lockdown 5 by Way */
-#define XPSS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930 /* Cache Data Lockdown 6 by Way */
-#define XPSS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934 /* Cache Instruction Lockdown 6 by Way */
-#define XPSS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938 /* Cache Data Lockdown 7 by Way */
-#define XPSS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093C /* Cache Instruction Lockdown 7 by Way */
-
-#define XPSS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950 /* Cache Lockdown Line Enable */
-#define XPSS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954 /* Cache Unlock All Lines by Way */
-
-#define XPSS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00 /* Start of address filtering */
-#define XPSS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04 /* Start of address filtering */
-
-#define XPSS_L2CC_DEBUG_CTRL_OFFSET 0x0F40 /* Debug Control Register */
-
-/* XPSS_L2CC_CNTRL_OFFSET bit position */
-
-#define XPSS_L2CC_ENABLE_MASK 0x00000001 /* enables the L2CC */
-
-/* XPSS_L2CC_AUX_CNTRL_OFFSET bit positions */
-
-#define XPSS_L2CC_AUX_IPFE_MASK 0x20000000 /* Instruction Prefetch Enable */
-#define XPSS_L2CC_AUX_DPFE_MASK 0x10000000 /* Data Prefetch Enable */
-#define XPSS_L2CC_AUX_NSIC_MASK 0x08000000 /* Non-secure interrupt access control */
-#define XPSS_L2CC_AUX_NSLE_MASK 0x04000000 /* Non-secure lockdown enable */
-#define XPSS_L2CC_AUX_FWE_MASK 0x01800000 /* Force write allocate */
-#define XPSS_L2CC_AUX_SAOE_MASK 0x00400000 /* Shared attribute override enable */
-#define XPSS_L2CC_AUX_PE_MASK 0x00200000 /* Parity enable */
-#define XPSS_L2CC_AUX_EMBE_MASK 0x00100000 /* Event monitor bus enable */
-#define XPSS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000 /* Way-size - s/b b100 for DF */
-#define XPSS_L2CC_AUX_ASSOC_MASK 0x00010000 /* Associativity */
-#define XPSS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000 /* Exclusive cache configuration */
-
-#define XPSS_L2CC_AUX_REG_DEFAULT_MASK 0x02020000 /* 16k*/
-#define XPSS_L2CC_AUX_REG_ZERO_MASK 0xFDF1FEFF /* */
-
-#define XPSS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000666 /* 7 Cycles of latency for TAG RAM s/b 0x00000111 for 2 */
-#define XPSS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000666 /* 7 Cycles of latency for DATA RAM s/b 0x00000111 for 2 */
-
-/* Interrupt bit positions */
-
-#define XPSS_L2CC_IXR_DECERR_MASK 0x00000100 /* DECERR from L3 */
-#define XPSS_L2CC_IXR_SLVERR_MASK 0x00000080 /* SLVERR from L3 */
-#define XPSS_L2CC_IXR_ERRRD_MASK 0x00000040 /* Error on L2 data RAM (Read) */
-#define XPSS_L2CC_IXR_ERRRT_MASK 0x00000020 /* Error on L2 tag RAM (Read) */
-#define XPSS_L2CC_IXR_ERRWD_MASK 0x00000010 /* Error on L2 data RAM (Write) */
-#define XPSS_L2CC_IXR_ERRWT_MASK 0x00000008 /* Error on L2 tag RAM (Write) */
-#define XPSS_L2CC_IXR_PARRD_MASK 0x00000004 /* Parity Error on L2 data RAM (Read) */
-#define XPSS_L2CC_IXR_PARRT_MASK 0x00000002 /* Parity Error on L2 tag RAM (Read) */
-#define XPSS_L2CC_IXR_ECNTR_MASK 0x00000001 /* Event Counter1/0 Overflow Increment */
-
-/* Address filtering mask and enable bit */
-
-#define XPSS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000 /* Address filtering valid bits*/
-#define XPSS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001 /* Address filtering enable bit*/
-
-/* Debug control bits */
-
-#define XPSS_L2CC_DEBUG_SPIDEN_MASK 0x00000004 /* Debug SPIDEN bit */
-#define XPSS_L2CC_DEBUG_DWB_MASK 0x00000002 /* Debug DWB bit, forces write through */
-#define XPSS_L2CC_DEBUG_DCL_MASK 0x00000002 /* Debug DCL bit, disables cache line fill */
+#define XPSS_L2CC_IER_OFFSET 0x0214 /* Interrupt Mask */
+#define XPSS_L2CC_IPR_OFFSET 0x0218 /* Masked interrupt status */
+#define XPSS_L2CC_ISR_OFFSET 0x021C /* Raw Interrupt Status */
+#define XPSS_L2CC_IAR_OFFSET 0x0220 /* Interrupt Clear */
+
+#define XPSS_L2CC_CACHE_SYNC_OFFSET 0x0730 /* Cache Sync */
+#define XPSS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770 /* Cache Invalid by PA */
+#define XPSS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077C /* Cache Invalid by Way */
+#define XPSS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0 /* Cache Clean by PA */
+#define XPSS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8 /* Cache Clean by Index */
+#define XPSS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BC /* Cache Clean by Way */
+#define XPSS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0 /* Cache Invalidate and Clean by PA */
+#define XPSS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8 /* Cache Invalidate and Clean by Index */
+#define XPSS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FC /* Cache Invalidate and Clean by Way */
+
+
+#define XPSS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900 /* Cache Data Lockdown 0 by Way */
+#define XPSS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904 /* Cache Instruction Lockdown 0 by Way */
+#define XPSS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908 /* Cache Data Lockdown 1 by Way */
+#define XPSS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090C /* Cache Instruction Lockdown 1 by Way */
+#define XPSS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910 /* Cache Data Lockdown 2 by Way */
+#define XPSS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914 /* Cache Instruction Lockdown 2 by Way */
+#define XPSS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918 /* Cache Data Lockdown 3 by Way */
+#define XPSS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091C /* Cache Instruction Lockdown 3 by Way */
+#define XPSS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920 /* Cache Data Lockdown 4 by Way */
+#define XPSS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924 /* Cache Instruction Lockdown 4 by Way */
+#define XPSS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928 /* Cache Data Lockdown 5 by Way */
+#define XPSS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092C /* Cache Instruction Lockdown 5 by Way */
+#define XPSS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930 /* Cache Data Lockdown 6 by Way */
+#define XPSS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934 /* Cache Instruction Lockdown 6 by Way */
+#define XPSS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938 /* Cache Data Lockdown 7 by Way */
+#define XPSS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093C /* Cache Instruction Lockdown 7 by Way */
+
+#define XPSS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950 /* Cache Lockdown Line Enable */
+#define XPSS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954 /* Cache Unlock All Lines by Way */
+
+#define XPSS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00 /* Start of address filtering */
+#define XPSS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04 /* Start of address filtering */
+
+#define XPSS_L2CC_DEBUG_CTRL_OFFSET 0x0F40 /* Debug Control Register */
+
+/* XPSS_L2CC_CNTRL_OFFSET bit position */
+#define XPSS_L2CC_ENABLE_MASK 0x00000001 /* enables the L2CC */
+
+/* XPSS_L2CC_AUX_CNTRL_OFFSET bit positions */
+#define XPSS_L2CC_AUX_IPFE_MASK 0x20000000 /* Instruction Prefetch Enable */
+#define XPSS_L2CC_AUX_DPFE_MASK 0x10000000 /* Data Prefetch Enable */
+#define XPSS_L2CC_AUX_NSIC_MASK 0x08000000 /* Non-secure interrupt access control */
+#define XPSS_L2CC_AUX_NSLE_MASK 0x04000000 /* Non-secure lockdown enable */
+#define XPSS_L2CC_AUX_FWE_MASK 0x01800000 /* Force write allocate */
+#define XPSS_L2CC_AUX_SAOE_MASK 0x00400000 /* Shared attribute override enable */
+#define XPSS_L2CC_AUX_PE_MASK 0x00200000 /* Parity enable */
+#define XPSS_L2CC_AUX_EMBE_MASK 0x00100000 /* Event monitor bus enable */
+#define XPSS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000 /* Way-size - s/b b100 for DF */
+#define XPSS_L2CC_AUX_ASSOC_MASK 0x00010000 /* Associativity */
+#define XPSS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000 /* Exclusive cache configuration */
+
+#define XPSS_L2CC_AUX_REG_DEFAULT_MASK 0x02020000 /* 16k*/
+#define XPSS_L2CC_AUX_REG_ZERO_MASK 0xFDF1FEFF /* */
+
+#define XPSS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000666 /* 7 Cycles of latency for TAG RAM s/b 0x00000111 for 2 */
+#define XPSS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000666 /* 7 Cycles of latency for DATA RAM s/b 0x00000111 for 2 */
+
+/* Interrupt bit positions */
+#define XPSS_L2CC_IXR_DECERR_MASK 0x00000100 /* DECERR from L3 */
+#define XPSS_L2CC_IXR_SLVERR_MASK 0x00000080 /* SLVERR from L3 */
+#define XPSS_L2CC_IXR_ERRRD_MASK 0x00000040 /* Error on L2 data RAM (Read) */
+#define XPSS_L2CC_IXR_ERRRT_MASK 0x00000020 /* Error on L2 tag RAM (Read) */
+#define XPSS_L2CC_IXR_ERRWD_MASK 0x00000010 /* Error on L2 data RAM (Write) */
+#define XPSS_L2CC_IXR_ERRWT_MASK 0x00000008 /* Error on L2 tag RAM (Write) */
+#define XPSS_L2CC_IXR_PARRD_MASK 0x00000004 /* Parity Error on L2 data RAM (Read) */
+#define XPSS_L2CC_IXR_PARRT_MASK 0x00000002 /* Parity Error on L2 tag RAM (Read) */
+#define XPSS_L2CC_IXR_ECNTR_MASK 0x00000001 /* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPSS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000 /* Address filtering valid bits*/
+#define XPSS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001 /* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPSS_L2CC_DEBUG_SPIDEN_MASK 0x00000004 /* Debug SPIDEN bit */
+#define XPSS_L2CC_DEBUG_DWB_MASK 0x00000002 /* Debug DWB bit, forces write through */
+#define XPSS_L2CC_DEBUG_DCL_MASK 0x00000002 /* Debug DCL bit, disables cache line fill */
+
+
+/* SCU register offsets */
+
+#define XPSS_SCU_CONTROL_OFFSET 0x000
+#define XPSS_SCU_CONFIG_OFFSET 0x004
+#define XPSS_SCU_FILTER_START_OFFSET 0x040
+#define XPSS_SCU_FILTER_END_OFFSET 0x044
+#define XPSS_SCU_NON_SECURE_ACCESS_OFFSET 0x054
#ifdef __cplusplus
}
-#endif
+#endif /* __cplusplus */
#endif /* protection macro */
projects / thirdparty / u-boot.git / commitdiff
