fpga: zynqpl: Correct PL bitstream loading sequence for zynqaes

Correct the PL bitstream loading sequence for zynqaes command by
clearing the loaded PL bitstream before loading the new encrypted
bitstream using the zynq aes command. This was done by setting
the PROG_B same as in case of fpgaload commands.
This patch fixes the issue of loading the encrypted PL bitstream
onto the PL in which a bitstream has already been loaded
succesfully.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/common/cmd_zynq_rsa.c b/common/cmd_zynq_rsa.c
index 261288209c6c811bdc1890c338b6fd4117a27138..b8e148e975b3bf507f17343f3b4de4b721748cb4 100644 (file)
--- a/common/cmd_zynq_rsa.c
+++ b/common/cmd_zynq_rsa.c
@@ -14,6 +14,7 @@
 #include <u-boot/sha256.h>
 #include <spi_flash.h>
 #include <zynqpl.h>
+#include <fpga.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -553,7 +554,8 @@ static int do_zynq_verify_image(cmd_tbl_t *cmdtp, int flag, int argc,
                                status = zynq_decrypt_load(part_load_addr,
                                                           part_img_len,
                                                           part_load_addr,
-                                                          part_data_len);
+                                                          part_data_len,
+                                                          BIT_NONE);
                                if (status != 0) {
                                        printf("DECRYPTION_FAIL\r\n");
                                        return -1;

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 22c715f8d7f8f8a4cfd705f0f75e9b9a31fb8a34..16a795d84ed1dd398e7a49a10c9b97976f49a73f 100644 (file)
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -204,7 +204,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype)
        /* Clear loopback bit */
        clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
 
-       if (bstype != BIT_PARTIAL) {
+       if (bstype != BIT_PARTIAL && bstype != BIT_NONE) {
                zynq_slcr_devcfg_disable();
 
                /* Setting PCFG_PROG_B signal to high */
@@ -500,60 +500,20 @@ struct xilinx_fpga_op zynq_op = {
  * Load the encrypted image from src addr and decrypt the image and
  * place it back the decrypted image into dstaddr.
  */
-int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
+int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
+                     u8 bstype)
 {
-       u32 isr_status, status;
-
        if ((srcaddr < SZ_1M) || (dstaddr < SZ_1M)) {
                printf("%s: src and dst addr should be > 1M\n",
                       __func__);
                return FPGA_FAIL;
        }
 
-       isr_status = readl(&devcfg_base->int_sts);
-
-       /* Clear it all, so if Boot ROM comes back, it can proceed */
-       writel(0xFFFFFFFF, &devcfg_base->int_sts);
-
-       if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
-               debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
-
-               /* If RX FIFO overflow, need to flush RX FIFO first */
-               if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
-                       writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
-                       writel(0xFFFFFFFF, &devcfg_base->int_sts);
-               }
+       if (zynq_dma_xfer_init(bstype)) {
+               printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
                return FPGA_FAIL;
        }
 
-       status = readl(&devcfg_base->status);
-
-       debug("%s: Status = 0x%08X\n", __func__, status);
-
-       if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
-               printf("%s: Error: device busy\n", __func__);
-               return FPGA_FAIL;
-       }
-
-       debug("%s: Device ready\n", __func__);
-
-       if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
-               if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
-                       /* Error state, transfer cannot occur */
-                       printf("%s: ISR indicates error\n", __func__);
-                       return FPGA_FAIL;
-               } else {
-                       /* Clear out the status */
-                       writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
-               }
-       }
-
-       if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
-               /* Clear the count of completed DMA transfers */
-               writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
-       }
-
-       clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
        writel((readl(&devcfg_base->ctrl) | DEVCFG_CTRL_PCAP_RATE_EN_MASK),
               &devcfg_base->ctrl);
 
@@ -579,6 +539,7 @@ static int do_zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc,
        u32 srclen;
        u32 dstaddr;
        u32 dstlen;
+       u8 imgtype = BIT_NONE;
        int status;
 
        if (argc < 5)
@@ -597,7 +558,10 @@ static int do_zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc,
        if (*argv[4] == 0 || *endp != 0)
                return -1;
 
-       status = zynq_decrypt_load(srcaddr, srclen, dstaddr, dstlen);
+       if (dstaddr == 0xFFFFFFFF)
+               imgtype = BIT_FULL;
+
+       status = zynq_decrypt_load(srcaddr, srclen, dstaddr, dstlen, imgtype);
        if (status != 0)
                return -1;
 

diff --git a/include/zynqpl.h b/include/zynqpl.h
index 11c87435fb21e73512bdb12d1a98b7db1d1dceb9..2ef6446e1116fe58471607f792a1f6c5fb59f702 100644 (file)
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -13,7 +13,8 @@
 #include <xilinx.h>
 
 #ifdef CONFIG_CMD_ZYNQ_AES
-extern int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen);
+extern int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen,
+                            u8 bstype);
 #endif
 #if defined(CONFIG_FPGA_ZYNQPL)
 extern struct xilinx_fpga_op zynq_op;