EDAC/amd64: Remove NUM_CONTROLLERS macro

Currently, the NUM_CONTROLLERS macro is used to limit the amount of memory
controllers (UMCs) available per node. The number of UMCs available per node,
however, is already cached by the max_mcs variable of struct amd64_pvt.

Allocate the relevant data structures dynamically using the variable instead
of static allocation through the macro.

The max_mcs variable is used for legacy systems too. These systems have a max
of 2 controllers. Since the default value of max_mcs, set in per_family_init(),
is 2, these legacy systems are also covered.

Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/20251106015727.1987246-1-avadhut.naik@amd.com

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 886ad075d222284211fe177cd9c7d539e3644fdd..2391f3469961ab20b968188fc4b2b68fa83c541c 100644 (file)
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3732,6 +3732,7 @@ static void hw_info_put(struct amd64_pvt *pvt)
        pci_dev_put(pvt->F1);
        pci_dev_put(pvt->F2);
        kfree(pvt->umc);
+       kfree(pvt->csels);
 }
 
 static struct low_ops umc_ops = {
@@ -3915,6 +3916,10 @@ static int per_family_init(struct amd64_pvt *pvt)
                scnprintf(pvt->ctl_name, sizeof(pvt->ctl_name), "F%02Xh_M%02Xh",
                          pvt->fam, pvt->model);
 
+       pvt->csels = kcalloc(pvt->max_mcs, sizeof(*pvt->csels), GFP_KERNEL);
+       if (!pvt->csels)
+               return -ENOMEM;
+
        return 0;
 }
 

diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 4ec6133d5179b1a11697a2085b22a2ba60828051..1757c1b99fc850a83f8d2f4ca9992fb369e09980 100644 (file)
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -96,7 +96,6 @@
 /* Hardware limit on ChipSelect rows per MC and processors per system */
 #define NUM_CHIPSELECTS                        8
 #define DRAM_RANGES                    8
-#define NUM_CONTROLLERS                        16
 
 #define ON true
 #define OFF false
@@ -348,7 +347,7 @@ struct amd64_pvt {
        u32 dbam1;              /* DRAM Base Address Mapping reg for DCT1 */
 
        /* one for each DCT/UMC */
-       struct chip_select csels[NUM_CONTROLLERS];
+       struct chip_select *csels;
 
        /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
        struct dram_range ranges[DRAM_RANGES];