drm/xe/guc: Eliminate RPa frequency caching

Remove the cached pc->rpa_freq field and refactor RPA frequency handling
to fetch values directly from hardware registers on each request.

v2: Check graphics version instead of platform (Rodrigo)
v3: Fix graphics version check (Badal)

Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Suggested-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Sk Anirban <sk.anirban@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/20251112185153.3593145-6-sk.anirban@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 4c48115f17951744bc5b98be765f7617ee0b197f..951a49fb1d3e4970fb8e433e4f23285b0e435047 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -363,7 +363,7 @@ static int pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
                                   freq);
 }
 
-static void mtl_update_rpa_value(struct xe_guc_pc *pc)
+static u32 mtl_get_rpa_freq(struct xe_guc_pc *pc)
 {
        struct xe_gt *gt = pc_to_gt(pc);
        u32 reg;
@@ -373,7 +373,7 @@ static void mtl_update_rpa_value(struct xe_guc_pc *pc)
        else
                reg = xe_mmio_read32(&gt->mmio, MTL_GT_RPA_FREQUENCY);
 
-       pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg));
+       return decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg));
 }
 
 static u32 mtl_get_rpe_freq(struct xe_guc_pc *pc)
@@ -389,24 +389,28 @@ static u32 mtl_get_rpe_freq(struct xe_guc_pc *pc)
        return decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
 }
 
-static void tgl_update_rpa_value(struct xe_guc_pc *pc)
+static u32 pvc_get_rpa_freq(struct xe_guc_pc *pc)
 {
-       struct xe_gt *gt = pc_to_gt(pc);
-       struct xe_device *xe = gt_to_xe(gt);
-       u32 reg;
-
        /*
         * For PVC we still need to use fused RP0 as the approximation for RPa
         * For other platforms than PVC we get the resolved RPa directly from
         * PCODE at a different register
         */
-       if (xe->info.platform == XE_PVC) {
-               reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
-               pc->rpa_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
-       } else {
-               reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
-               pc->rpa_freq = REG_FIELD_GET(RPA_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
-       }
+
+       struct xe_gt *gt = pc_to_gt(pc);
+       u32 reg;
+
+       reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
+       return REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
+}
+
+static u32 tgl_get_rpa_freq(struct xe_guc_pc *pc)
+{
+       struct xe_gt *gt = pc_to_gt(pc);
+       u32 reg;
+
+       reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
+       return REG_FIELD_GET(RPA_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
 }
 
 static u32 pvc_get_rpe_freq(struct xe_guc_pc *pc)
@@ -434,17 +438,6 @@ static u32 tgl_get_rpe_freq(struct xe_guc_pc *pc)
        return REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
 }
 
-static void pc_update_rp_values(struct xe_guc_pc *pc)
-{
-       struct xe_gt *gt = pc_to_gt(pc);
-       struct xe_device *xe = gt_to_xe(gt);
-
-       if (GRAPHICS_VERx100(xe) >= 1270)
-               mtl_update_rpa_value(pc);
-       else
-               tgl_update_rpa_value(pc);
-}
-
 /**
  * xe_guc_pc_get_act_freq - Get Actual running frequency
  * @pc: The GuC PC
@@ -543,9 +536,15 @@ u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc)
  */
 u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc)
 {
-       pc_update_rp_values(pc);
+       struct xe_gt *gt = pc_to_gt(pc);
+       struct xe_device *xe = gt_to_xe(gt);
 
-       return pc->rpa_freq;
+       if (GRAPHICS_VERx100(xe) == 1260)
+               return pvc_get_rpa_freq(pc);
+       else if (GRAPHICS_VERx100(xe) >= 1270)
+               return mtl_get_rpa_freq(pc);
+       else
+               return tgl_get_rpa_freq(pc);
 }
 
 /**
@@ -1136,8 +1135,6 @@ static int pc_init_freqs(struct xe_guc_pc *pc)
        if (ret)
                goto out;
 
-       pc_update_rp_values(pc);
-
        pc_init_pcode_freq(pc);
 
        /*

diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h b/drivers/gpu/drm/xe/xe_guc_pc_types.h
index f27c05d8170656c58ff5b933acf009e61deb59fc..711bbcdcb0d320c91f452822cbc77aacf2aa2078 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
@@ -19,8 +19,6 @@ struct xe_guc_pc {
        atomic_t flush_freq_limit;
        /** @rp0_freq: HW RP0 frequency - The Maximum one */
        u32 rp0_freq;
-       /** @rpa_freq: HW RPa frequency - The Achievable one */
-       u32 rpa_freq;
        /** @rpn_freq: HW RPN frequency - The Minimum one */
        u32 rpn_freq;
        /** @user_requested_min: Stash the minimum requested freq by user */