rs6000.c (rs6000_dwarf_register_span): Fix debug output for other floating point...

	* config/rs6000/rs6000.c (rs6000_dwarf_register_span): Fix debug
	output for other floating point modes.

From-SVN: r146060

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eae509530ca1f5f4ad17e00d09c74d708ef17c92..cbdc1a48176f1c3e268edbe97c0fad31639b9730 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2009-04-14  Daniel Jacobowitz  <dan@codesourcery.com>
+
+       * config/rs6000/rs6000.c (rs6000_dwarf_register_span): Fix debug
+       output for other floating point modes.
+
 2009-04-14  Diego Novillo  <dnovillo@google.com>
            Le-Chun Wu  <lcwu@google.com>
 

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 235298935c3ef04d0bed64cac38925163dc290b1..9035d13451b494028c961e05e09d840240000b49 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -22689,12 +22689,16 @@ rs6000_is_opaque_type (const_tree type)
 static rtx
 rs6000_dwarf_register_span (rtx reg)
 {
-  unsigned regno;
+  rtx parts[8];
+  int i, words;
+  unsigned regno = REGNO (reg);
+  enum machine_mode mode = GET_MODE (reg);
 
   if (TARGET_SPE
+      && regno < 32
       && (SPE_VECTOR_MODE (GET_MODE (reg))
-         || (TARGET_E500_DOUBLE
-             && (GET_MODE (reg) == DFmode || GET_MODE (reg) == DDmode))))
+         || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
+             && mode != SFmode && mode != SDmode && mode != SCmode)))
     ;
   else
     return NULL_RTX;
@@ -22704,15 +22708,23 @@ rs6000_dwarf_register_span (rtx reg)
   /* The duality of the SPE register size wreaks all kinds of havoc.
      This is a way of distinguishing r0 in 32-bits from r0 in
      64-bits.  */
-  return
-    gen_rtx_PARALLEL (VOIDmode,
-                     BYTES_BIG_ENDIAN
-                     ? gen_rtvec (2,
-                                  gen_rtx_REG (SImode, regno + 1200),
-                                  gen_rtx_REG (SImode, regno))
-                     : gen_rtvec (2,
-                                  gen_rtx_REG (SImode, regno),
-                                  gen_rtx_REG (SImode, regno + 1200)));
+  words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
+  gcc_assert (words <= 4);
+  for (i = 0; i < words; i++, regno++)
+    {
+      if (BYTES_BIG_ENDIAN)
+       {
+         parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
+         parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
+       }
+      else
+       {
+         parts[2 * i] = gen_rtx_REG (SImode, regno);
+         parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
+       }
+    }
+
+  return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts));
 }
 
 /* Fill in sizes for SPE register high parts in table used by unwinder.  */