arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC

As per C3 datasheet add missing cache information to the Amlogic C3 SoC.

- Each Cortex-A53 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.

Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-9-linux.amoon@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
index b81bffac77324024e82864adbda05b7707266673..e8529e8c4b153ba622f05d801b5205170cb82bc8 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
@@ -23,6 +23,13 @@
                        compatible = "arm,cortex-a35";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2>;
                };
 
                cpu1: cpu@1 {
@@ -30,6 +37,22 @@
                        compatible = "arm,cortex-a35";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2>;
+               };
+
+               l2: l2-cache0 {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+                       cache-size = <0x7d000>; /* L2. 512 KB */
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
                };
        };