drm/amd/display: Rename FAMS2 global control lock to DMUB HW control lock

[Why]
FAMS2 dictates whether the inbox0 HW lock is required, but it is not the
only feature that may determine this.

In order to leverage the faster inbox0 HW lock in place of the inbox1
ringbuffer based control lock it's desirable to utilize the HWSS
based locking protocol FAMS2 has already implemented.

[How]
Rename the FAMS2 global control lock to DMUB HW control lock.

This is purely a refactor with no functional change, the logic that will
determine which features need to enable this HW lock will be added in a
future commit.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index be885801a9ed69c2412ad5881c6a54c740cae308..eae2dabd5182c476f7a3a8a9a7cb68d4c688ed3b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2158,8 +2158,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
         */
        if (dc->hwss.subvp_pipe_control_lock)
                dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);
-       if (dc->hwss.fams2_global_control_lock)
-               dc->hwss.fams2_global_control_lock(dc, context, true);
+       if (dc->hwss.dmub_hw_control_lock)
+               dc->hwss.dmub_hw_control_lock(dc, context, true);
 
        if (dc->hwss.update_dsc_pg)
                dc->hwss.update_dsc_pg(dc, context, false);
@@ -2229,8 +2229,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
                dc->hwss.commit_subvp_config(dc, context);
        if (dc->hwss.subvp_pipe_control_lock)
                dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use);
-       if (dc->hwss.fams2_global_control_lock)
-               dc->hwss.fams2_global_control_lock(dc, context, false);
+       if (dc->hwss.dmub_hw_control_lock)
+               dc->hwss.dmub_hw_control_lock(dc, context, false);
 
        for (i = 0; i < context->stream_count; i++) {
                const struct dc_link *link = context->streams[i]->link;
@@ -4176,16 +4176,16 @@ static void commit_planes_for_stream(struct dc *dc,
                if (dc->hwss.subvp_pipe_control_lock)
                        dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);
 
-               if (dc->hwss.fams2_global_control_lock)
-                       dc->hwss.fams2_global_control_lock(dc, context, true);
+               if (dc->hwss.dmub_hw_control_lock)
+                       dc->hwss.dmub_hw_control_lock(dc, context, true);
 
                dc->hwss.interdependent_update_lock(dc, context, true);
        } else {
                if (dc->hwss.subvp_pipe_control_lock)
                        dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
 
-               if (dc->hwss.fams2_global_control_lock)
-                       dc->hwss.fams2_global_control_lock(dc, context, true);
+               if (dc->hwss.dmub_hw_control_lock)
+                       dc->hwss.dmub_hw_control_lock(dc, context, true);
 
                /* Lock the top pipe while updating plane addrs, since freesync requires
                 *  plane addr update event triggers to be synchronized.
@@ -4228,9 +4228,8 @@ static void commit_planes_for_stream(struct dc *dc,
                        dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes,
                                                         NULL, subvp_prev_use);
 
-               if (dc->hwss.fams2_global_control_lock)
-                       dc->hwss.fams2_global_control_lock(dc, context, false);
-
+               if (dc->hwss.dmub_hw_control_lock)
+                       dc->hwss.dmub_hw_control_lock(dc, context, false);
                return;
        }
 
@@ -4467,13 +4466,13 @@ static void commit_planes_for_stream(struct dc *dc,
        if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
                if (dc->hwss.subvp_pipe_control_lock)
                        dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);
-               if (dc->hwss.fams2_global_control_lock)
-                       dc->hwss.fams2_global_control_lock(dc, context, false);
+               if (dc->hwss.dmub_hw_control_lock)
+                       dc->hwss.dmub_hw_control_lock(dc, context, false);
        } else {
                if (dc->hwss.subvp_pipe_control_lock)
                        dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
-               if (dc->hwss.fams2_global_control_lock)
-                       dc->hwss.fams2_global_control_lock(dc, context, false);
+               if (dc->hwss.dmub_hw_control_lock)
+                       dc->hwss.dmub_hw_control_lock(dc, context, false);
        }
 
        // Fire manual trigger only when bottom plane is flipped

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index d82b1cb467f4b61e7637f86a2f63ed9d248514d2..25a07e5f4ed77b1aa9865f3eaf75da6c77d8da99 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -755,11 +755,11 @@ void hwss_build_fast_sequence(struct dc *dc,
                block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
                (*num_steps)++;
        }
-       if (dc->hwss.fams2_global_control_lock_fast) {
-               block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc;
-               block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = true;
-               block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);
-               block_sequence[*num_steps].func = DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST;
+       if (dc->hwss.dmub_hw_control_lock_fast) {
+               block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;
+               block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = true;
+               block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);
+               block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST;
                (*num_steps)++;
        }
        if (dc->hwss.pipe_control_lock) {
@@ -894,11 +894,11 @@ void hwss_build_fast_sequence(struct dc *dc,
                block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
                (*num_steps)++;
        }
-       if (dc->hwss.fams2_global_control_lock_fast) {
-               block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc;
-               block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = false;
-               block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);
-               block_sequence[*num_steps].func = DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST;
+       if (dc->hwss.dmub_hw_control_lock_fast) {
+               block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;
+               block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = false;
+               block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);
+               block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST;
                (*num_steps)++;
        }
 
@@ -1001,8 +1001,8 @@ void hwss_execute_sequence(struct dc *dc,
                                        params->wait_for_dcc_meta_propagation_params.dc,
                                        params->wait_for_dcc_meta_propagation_params.top_pipe_to_program);
                        break;
-               case DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST:
-                       dc->hwss.fams2_global_control_lock_fast(params);
+               case DMUB_HW_CONTROL_LOCK_FAST:
+                       dc->hwss.dmub_hw_control_lock_fast(params);
                        break;
                default:
                        ASSERT(false);

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 7c276c3190867f3ed1ab0356a029688dc4a2fd1f..ab21da435a36dd6d6df895439f310d4caf42a8a8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1404,9 +1404,9 @@ void dcn401_prepare_bandwidth(struct dc *dc,
        }
 
        if (dc->debug.fams2_config.bits.enable) {
-               dcn401_fams2_global_control_lock(dc, context, true);
+               dcn401_dmub_hw_control_lock(dc, context, true);
                dcn401_fams2_update_config(dc, context, false);
-               dcn401_fams2_global_control_lock(dc, context, false);
+               dcn401_dmub_hw_control_lock(dc, context, false);
        }
 
        if (p_state_change_support != context->bw_ctx.bw.dcn.clk.p_state_change_support) {
@@ -1425,9 +1425,9 @@ void dcn401_optimize_bandwidth(
 
        /* enable fams2 if needed */
        if (dc->debug.fams2_config.bits.enable) {
-               dcn401_fams2_global_control_lock(dc, context, true);
+               dcn401_dmub_hw_control_lock(dc, context, true);
                dcn401_fams2_update_config(dc, context, true);
-               dcn401_fams2_global_control_lock(dc, context, false);
+               dcn401_dmub_hw_control_lock(dc, context, false);
        }
 
        /* program dchubbub watermarks */
@@ -1466,7 +1466,7 @@ void dcn401_optimize_bandwidth(
        }
 }
 
-void dcn401_fams2_global_control_lock(struct dc *dc,
+void dcn401_dmub_hw_control_lock(struct dc *dc,
                struct dc_state *context,
                bool lock)
 {
@@ -1483,12 +1483,12 @@ void dcn401_fams2_global_control_lock(struct dc *dc,
        dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
 }
 
-void dcn401_fams2_global_control_lock_fast(union block_sequence_params *params)
+void dcn401_dmub_hw_control_lock_fast(union block_sequence_params *params)
 {
-       struct dc *dc = params->fams2_global_control_lock_fast_params.dc;
-       bool lock = params->fams2_global_control_lock_fast_params.lock;
+       struct dc *dc = params->dmub_hw_control_lock_fast_params.dc;
+       bool lock = params->dmub_hw_control_lock_fast_params.lock;
 
-       if (params->fams2_global_control_lock_fast_params.is_required) {
+       if (params->dmub_hw_control_lock_fast_params.is_required) {
                union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
 
                hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
index 2621b7725267edaef56cc4a2e539c33733e98639..9591657d8eee3174f0b68cd797e5cdde26a0f545 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
@@ -73,11 +73,11 @@ void dcn401_optimize_bandwidth(
                struct dc *dc,
                struct dc_state *context);
 
-void dcn401_fams2_global_control_lock(struct dc *dc,
+void dcn401_dmub_hw_control_lock(struct dc *dc,
                struct dc_state *context,
                bool lock);
 void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable);
-void dcn401_fams2_global_control_lock_fast(union block_sequence_params *params);
+void dcn401_dmub_hw_control_lock_fast(union block_sequence_params *params);
 void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings);
 void dcn401_hardware_release(struct dc *dc);
 void dcn401_update_odm(struct dc *dc, struct dc_state *context,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index d6e11b7e4fcefd936db6655406c35e1395e13207..a221b8cb6d4dd3ebeef7514801f34c7551fafb56 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -95,9 +95,9 @@ static const struct hw_sequencer_funcs dcn401_funcs = {
        .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom,
        .wait_for_dcc_meta_propagation = dcn401_wait_for_dcc_meta_propagation,
        .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless,
-       .fams2_global_control_lock = dcn401_fams2_global_control_lock,
+       .dmub_hw_control_lock = dcn401_dmub_hw_control_lock,
        .fams2_update_config = dcn401_fams2_update_config,
-       .fams2_global_control_lock_fast = dcn401_fams2_global_control_lock_fast,
+       .dmub_hw_control_lock_fast = dcn401_dmub_hw_control_lock_fast,
        .program_outstanding_updates = dcn401_program_outstanding_updates,
        .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates,
        .detect_pipe_changes = dcn401_detect_pipe_changes,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index 1723bbcf2c46a08f939f892e9358a9dd60e78fb1..619ac4dfff078574373fe351df4c42dc7f2ffb09 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -148,7 +148,7 @@ struct wait_for_dcc_meta_propagation_params {
        const struct pipe_ctx *top_pipe_to_program;
 };
 
-struct fams2_global_control_lock_fast_params {
+struct dmub_hw_control_lock_fast_params {
        struct dc *dc;
        bool is_required;
        bool lock;
@@ -173,7 +173,7 @@ union block_sequence_params {
        struct set_ocsc_default_params set_ocsc_default_params;
        struct subvp_save_surf_addr subvp_save_surf_addr;
        struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params;
-       struct fams2_global_control_lock_fast_params fams2_global_control_lock_fast_params;
+       struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params;
 };
 
 enum block_sequence_func {
@@ -195,7 +195,7 @@ enum block_sequence_func {
        MPC_SET_OCSC_DEFAULT,
        DMUB_SUBVP_SAVE_SURF_ADDR,
        HUBP_WAIT_FOR_DCC_META_PROP,
-       DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST,
+       DMUB_HW_CONTROL_LOCK_FAST,
        /* This must be the last value in this enum, add new ones above */
        HWSS_BLOCK_SEQUENCE_FUNC_COUNT
 };
@@ -452,13 +452,13 @@ struct hw_sequencer_funcs {
                        const struct dc_state *new_ctx);
        void (*wait_for_dcc_meta_propagation)(const struct dc *dc,
                const struct pipe_ctx *top_pipe_to_program);
-       void (*fams2_global_control_lock)(struct dc *dc,
+       void (*dmub_hw_control_lock)(struct dc *dc,
                        struct dc_state *context,
                        bool lock);
        void (*fams2_update_config)(struct dc *dc,
                        struct dc_state *context,
                        bool enable);
-       void (*fams2_global_control_lock_fast)(union block_sequence_params *params);
+       void (*dmub_hw_control_lock_fast)(union block_sequence_params *params);
        void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max);
        void (*program_outstanding_updates)(struct dc *dc,
                        struct dc_state *context);