return intel_display_needs_wa_16023588340(display);
case INTEL_DISPLAY_WA_16025573575:
return intel_display_needs_wa_16025573575(display);
+ case INTEL_DISPLAY_WA_18034343758:
+ return DISPLAY_VER(display) == 20 ||
+ (display->platform.pantherlake &&
+ IS_DISPLAY_STEP(display, STEP_A0, STEP_B0));
case INTEL_DISPLAY_WA_22010178259:
return DISPLAY_VER(display) == 12;
case INTEL_DISPLAY_WA_22011320316:
INTEL_DISPLAY_WA_16011863758,
INTEL_DISPLAY_WA_16023588340,
INTEL_DISPLAY_WA_16025573575,
+ INTEL_DISPLAY_WA_18034343758,
INTEL_DISPLAY_WA_22010178259,
INTEL_DISPLAY_WA_22011320316,
INTEL_DISPLAY_WA_22012358565,
#include "intel_display_core.h"
#include "intel_display_types.h"
#include "intel_display_utils.h"
+#include "intel_display_wa.h"
#include "intel_dmc.h"
#include "intel_dmc_regs.h"
#include "intel_dsb.h"
intel_flipq_sw_dmc_wake(crtc);
}
-/* Wa_18034343758 */
-static bool need_dmc_halt_wa(struct intel_display *display)
-{
- return DISPLAY_VER(display) == 20 ||
- (display->platform.pantherlake &&
- IS_DISPLAY_STEP(display, STEP_A0, STEP_B0));
-}
-
void intel_flipq_wait_dmc_halt(struct intel_dsb *dsb, struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(crtc);
- if (need_dmc_halt_wa(display))
+ if (intel_display_wa(display, INTEL_DISPLAY_WA_18034343758))
intel_dsb_wait_usec(dsb, 2);
}
{
struct intel_display *display = to_intel_display(crtc);
- if (need_dmc_halt_wa(display))
+ if (intel_display_wa(display, INTEL_DISPLAY_WA_18034343758))
intel_dsb_reg_write(dsb, PIPEDMC_CTL(crtc->pipe), 0);
}