Correct the latency of loads in M5100

gcc/
	* config/mips/m5100.md (m51_int_load): Update the latency to 2.

From-SVN: r236288

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4ecd3e7919eaf250bf325fb2005d3f6b871c0b81..02f38cf536fb4eb5407ca57a44cd84cc72a952ae 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2016-05-16  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * config/mips/m5100.md (m51_int_load): Update the latency to 2.
+
 2016-05-16  Nathan Sidwell  <nathan@acm.org>
 
        * config/nvptx/nvptx.c (nvptx_mangle_decl_assembler_name): Revert.

diff --git a/gcc/config/mips/m5100.md b/gcc/config/mips/m5100.md
index f69fc7fc60994c549496e2ad2130ba6ffc8df0f8..8d87b7087fcc242d410abdb75f56e20f3014f49e 100644 (file)
--- a/gcc/config/mips/m5100.md
+++ b/gcc/config/mips/m5100.md
@@ -65,7 +65,7 @@
 
 ;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
 ;; prefetch: prefetch, prefetchx
-(define_insn_reservation "m51_int_load" 3
+(define_insn_reservation "m51_int_load" 2
   (and (eq_attr "cpu" "m5100")
        (eq_attr "type" "load,prefetch,prefetchx"))
   "m51_alu")