]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amdgpu: Add ras module ip block to amdgpu discovery
authorYiPeng Chai <YiPeng.Chai@amd.com>
Mon, 31 Mar 2025 03:12:58 +0000 (11:12 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 20 Oct 2025 22:25:54 +0000 (18:25 -0400)
Add ras module ip block to amdgpu discovery.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
drivers/gpu/drm/amd/include/amd_shared.h
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h

index 84c9ff86b49547f2f8b5319e799145261a95f4dc..a5574e84694ba6c3834d8aafa31a347ecb4e3e20 100644 (file)
@@ -380,7 +380,7 @@ int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block);
 
 int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block);
 
-#define AMDGPU_MAX_IP_NUM 16
+#define AMDGPU_MAX_IP_NUM AMD_IP_BLOCK_TYPE_NUM
 
 struct amdgpu_ip_block_status {
        bool valid;
index 4e75334f3b3a09522668ceafa7fa2c4b79798c4b..3097b2946682524dfdc9d55504dfb8b79f7bc89e 100644 (file)
 #include "vcn_v5_0_1.h"
 #include "jpeg_v5_0_0.h"
 #include "jpeg_v5_0_1.h"
+#include "amdgpu_ras_mgr.h"
 
 #include "amdgpu_vpe.h"
 #if defined(CONFIG_DRM_AMD_ISP)
@@ -2393,6 +2394,21 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
                        amdgpu_ip_version(adev, SDMA0_HWIP, 0));
                return -EINVAL;
        }
+
+       return 0;
+}
+
+static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev)
+{
+       switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
+       case IP_VERSION(13, 0, 6):
+       case IP_VERSION(13, 0, 12):
+       case IP_VERSION(13, 0, 14):
+               amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block);
+               break;
+       default:
+               break;
+       }
        return 0;
 }
 
@@ -3173,6 +3189,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
        if (r)
                return r;
 
+       r = amdgpu_discovery_set_ras_ip_blocks(adev);
+       if (r)
+               return r;
+
        if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
             !amdgpu_sriov_vf(adev)) ||
            (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
index 75efda2969cfb394d121112229102e18d6be3152..17945094a1383400061fd21144822252966d74d2 100644 (file)
@@ -109,6 +109,7 @@ enum amd_ip_block_type {
        AMD_IP_BLOCK_TYPE_VPE,
        AMD_IP_BLOCK_TYPE_UMSCH_MM,
        AMD_IP_BLOCK_TYPE_ISP,
+       AMD_IP_BLOCK_TYPE_RAS,
        AMD_IP_BLOCK_TYPE_NUM,
 };
 
index a8d02bd42f9085cc9f80a828438a41bdf36ab9f2..3ae843d078d85c65abfcbd75f42397b74a323a8e 100644 (file)
@@ -381,6 +381,14 @@ static const struct amd_ip_funcs __maybe_unused ras_v1_0_ip_funcs = {
        .hw_fini = amdgpu_ras_mgr_hw_fini,
 };
 
+const struct amdgpu_ip_block_version ras_v1_0_ip_block = {
+       .type = AMD_IP_BLOCK_TYPE_RAS,
+       .major = 1,
+       .minor = 0,
+       .rev = 0,
+       .funcs = &ras_v1_0_ip_funcs,
+};
+
 int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable)
 {
        struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev);
index 8d6a1873b6669c3b34fd76dfff843253d8ebaf52..814b65ef1c62e8cb611d9ded33399af93b231ca7 100644 (file)
@@ -54,6 +54,8 @@ struct amdgpu_ras_mgr {
        bool ras_is_ready;
 };
 
+extern const struct amdgpu_ip_block_version ras_v1_0_ip_block;
+
 struct amdgpu_ras_mgr *amdgpu_ras_mgr_get_context(
                        struct amdgpu_device *adev);
 int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable);