arm64: dts: qcom: qcs615: enable pcie

Add configurations in devicetree for PCIe0, including registers, clocks,
interrupts and phy setting sequence.

Add PCIe lane equalization preset properties for 8 GT/s.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250725112346.614316-2-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi
index e033b53f0f0f4200d4413c05c3d6cca6742f9415..6fa4614c13aeeab0242f8ac67364e9275d71e68d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi
@@ -1072,6 +1072,144 @@
                        qcom,bcm-voters = <&apps_bcm_voter>;
                };
 
+               pcie: pcie@1c08000 {
+                       device_type = "pci";
+                       compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150";
+                       reg = <0x0 0x01c08000 0x0 0x3000>,
+                             <0x0 0x40000000 0x0 0xf1d>,
+                             <0x0 0x40000f20 0x0 0xa8>,
+                             <0x0 0x40001000 0x0 0x1000>,
+                             <0x0 0x40100000 0x0 0x100000>,
+                             <0x0 0x01c0b000 0x0 0x1000>;
+                       reg-names = "parf",
+                                   "dbi",
+                                   "elbi",
+                                   "atu",
+                                   "config",
+                                   "mhi";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+                                <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+                       bus-range = <0x00 0xff>;
+
+                       dma-coherent;
+
+                       linux,pci-domain = <0>;
+                       num-lanes = <1>;
+
+                       interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi0",
+                                         "msi1",
+                                         "msi2",
+                                         "msi3",
+                                         "msi4",
+                                         "msi5",
+                                         "msi6",
+                                         "msi7",
+                                         "global";
+
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+                                <&gcc GCC_PCIE_0_AUX_CLK>,
+                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+                                <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+                                <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
+                       clock-names = "pipe",
+                                     "aux",
+                                     "cfg",
+                                     "bus_master",
+                                     "bus_slave",
+                                     "slave_q2a";
+                       assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
+                       assigned-clock-rates = <19200000>;
+
+                       interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       interconnect-names = "pcie-mem", "cpu-pcie";
+
+                       iommu-map = <0x0 &apps_smmu 0x400 0x1>,
+                                   <0x100 &apps_smmu 0x401 0x1>;
+
+                       resets = <&gcc GCC_PCIE_0_BCR>;
+                       reset-names = "pci";
+
+                       power-domains = <&gcc PCIE_0_GDSC>;
+
+                       phys = <&pcie_phy>;
+                       phy-names = "pciephy";
+
+                       max-link-speed = <2>;
+
+                       operating-points-v2 = <&pcie_opp_table>;
+
+                       status = "disabled";
+
+                       pcie_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               /* GEN 1 x1 */
+                               opp-2500000 {
+                                       opp-hz = /bits/ 64 <2500000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                                       opp-peak-kBps = <250000 1>;
+                               };
+
+                               /* GEN 2 x1 */
+                               opp-5000000 {
+                                       opp-hz = /bits/ 64 <5000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                                       opp-peak-kBps = <500000 1>;
+                               };
+                       };
+               };
+
+               pcie_phy: phy@1c0e000 {
+                       compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy";
+                       reg = <0x0 0x01c0e000 0x0 0x1000>;
+
+                       clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_0_CLKREF_CLK>,
+                                <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
+                                <&gcc GCC_PCIE_0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "cfg_ahb",
+                                     "ref",
+                                     "refgen",
+                                     "pipe";
+
+                       resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+                       reset-names = "phy";
+
+                       assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
+                       assigned-clock-rates = <100000000>;
+
+                       #clock-cells = <0>;
+                       clock-output-names = "pcie_0_pipe_clk";
+
+                       #phy-cells = <0>;
+
+                       status = "disabled";
+               };
+
                ufs_mem_hc: ufshc@1d84000 {
                        compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
                        reg = <0x0 0x01d84000 0x0 0x3000>,