5.4-stable patches

added patches:
	counter-stm32-lptimer-cnt-fix-error-handling-when-enabling.patch

diff --git a/queue-5.4/counter-stm32-lptimer-cnt-fix-error-handling-when-enabling.patch b/queue-5.4/counter-stm32-lptimer-cnt-fix-error-handling-when-enabling.patch
new file mode 100644 (file)
index 0000000..20f5ce5
--- /dev/null
+++ b/queue-5.4/counter-stm32-lptimer-cnt-fix-error-handling-when-enabling.patch
@@ -0,0 +1,87 @@
+From 8744dcd4fc7800de2eb9369410470bb2930d4c14 Mon Sep 17 00:00:00 2001
+From: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
+Date: Mon, 24 Feb 2025 18:06:57 +0100
+Subject: counter: stm32-lptimer-cnt: fix error handling when enabling
+
+From: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
+
+commit 8744dcd4fc7800de2eb9369410470bb2930d4c14 upstream.
+
+In case the stm32_lptim_set_enable_state() fails to update CMP and ARR,
+a timeout error is raised, by regmap_read_poll_timeout. It may happen,
+when the lptimer runs on a slow clock, and the clock is gated only
+few times during the polling.
+
+Badly, when this happen, STM32_LPTIM_ENABLE in CR register has been set.
+So the 'enable' state in sysfs wrongly lies on the counter being
+correctly enabled, due to CR is read as one in stm32_lptim_is_enabled().
+
+To fix both issues:
+- enable the clock before writing CMP, ARR and polling ISR bits. It will
+avoid the possible timeout error.
+- clear the ENABLE bit in CR and disable the clock in the error path.
+
+Fixes: d8958824cf07 ("iio: counter: Add support for STM32 LPTimer")
+Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
+Link: https://lore.kernel.org/r/20250224170657.3368236-1-fabrice.gasnier@foss.st.com
+Signed-off-by: William Breathitt Gray <wbg@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/counter/stm32-lptimer-cnt.c |   24 +++++++++++++++---------
+ 1 file changed, 15 insertions(+), 9 deletions(-)
+
+--- a/drivers/counter/stm32-lptimer-cnt.c
++++ b/drivers/counter/stm32-lptimer-cnt.c
+@@ -58,37 +58,43 @@ static int stm32_lptim_set_enable_state(
+               return 0;
+       }
+ 
++      ret = clk_enable(priv->clk);
++      if (ret)
++              goto disable_cnt;
++
+       /* LP timer must be enabled before writing CMP & ARR */
+       ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
+       if (ret)
+-              return ret;
++              goto disable_clk;
+ 
+       ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
+       if (ret)
+-              return ret;
++              goto disable_clk;
+ 
+       /* ensure CMP & ARR registers are properly written */
+       ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
+                                      (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK,
+                                      100, 1000);
+       if (ret)
+-              return ret;
++              goto disable_clk;
+ 
+       ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
+                          STM32_LPTIM_CMPOKCF_ARROKCF);
+       if (ret)
+-              return ret;
++              goto disable_clk;
+ 
+-      ret = clk_enable(priv->clk);
+-      if (ret) {
+-              regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
+-              return ret;
+-      }
+       priv->enabled = true;
+ 
+       /* Start LP timer in continuous mode */
+       return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
+                                 STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
++
++disable_clk:
++      clk_disable(priv->clk);
++disable_cnt:
++      regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
++
++      return ret;
+ }
+ 
+ static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)

diff --git a/queue-5.4/series b/queue-5.4/series
index da25de9e55ca8cf4d3ba635f9f145fbe9f7ea249..42ad1e19ea35baf5ba77d0e0ac23a4a15e8dcb17 100644 (file)
--- a/queue-5.4/series
+++ b/queue-5.4/series
@@ -70,3 +70,4 @@ arm-9350-1-fault-implement-copy_from_kernel_nofault_allowed.patch
 arm-9351-1-fault-add-cut-here-line-for-prefetch-aborts.patch
 arm-remove-address-checking-for-mmuless-devices.patch
 netfilter-socket-lookup-orig-tuple-for-ipv6-snat.patch
+counter-stm32-lptimer-cnt-fix-error-handling-when-enabling.patch