TCGv zero;
} DisasContext;
+static inline MemOp mo_endian(DisasContext *dc)
+{
+ return MO_TE;
+}
+
static inline bool is_user(DisasContext *dc)
{
#ifdef CONFIG_USER_ONLY
check_r0_write(dc, a->d);
ea = tcg_temp_new();
tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i);
- tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TE | MO_UL);
+ tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx,
+ mo_endian(dc) | MO_UL);
tcg_gen_mov_tl(cpu_lock_addr, ea);
tcg_gen_mov_tl(cpu_lock_value, cpu_R(dc, a->d));
return true;
{
TCGv ea;
- mop |= MO_TE;
+ mop |= mo_endian(dc);
check_r0_write(dc, a->d);
ea = tcg_temp_new();
val = tcg_temp_new();
tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value,
- cpu_R(dc, a->b), dc->mem_idx, MO_TE | MO_UL);
+ cpu_R(dc, a->b), dc->mem_idx,
+ mo_endian(dc) | MO_UL);
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value);
tcg_gen_br(lab_done);
{
TCGv t0 = tcg_temp_new();
- mop |= MO_TE;
+ mop |= mo_endian(dc);
tcg_gen_addi_tl(t0, cpu_R(dc, a->a), a->i);
tcg_gen_qemu_st_tl(cpu_R(dc, a->b), t0, dc->mem_idx, mop);