RISC-V: Add test cases for vzext.vf8 reg overlap

Add test cases for vzext.vf8 register group overlap, please
note it is not overlap as much as possible.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-m1.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-mf2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-mf4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-mf8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-m1.c
new file mode 100644 (file)
index 0000000..c0e233b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e8m1,
+  vuint8m1_t,
+  vuint64m8_t,
+  __riscv_vle8_v_u8m1,
+  __riscv_vzext_vf8_u64m8,
+  __riscv_vse64_v_u64m8,
+  vzext_vf,
+  LOOP_UNARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vzext\.vf8\s+v0,v7([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vzext\.vf8\s+v8,v15} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-mf2.c
new file mode 100644 (file)
index 0000000..f58c6cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf2_t,
+  vuint64m4_t,
+  __riscv_vle8_v_u8mf2,
+  __riscv_vzext_vf8_u64m4,
+  __riscv_vse64_v_u64m4,
+  vzext_vf,
+  LOOP_UNARY_BODY_X8)
+
+/* { dg-final { scan-assembler-not {vzext\.vf8\s+v0,v7([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf8\s+v8,v15} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf8\s+v16,v23} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf8\s+v24,v31} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-mf4.c
new file mode 100644 (file)
index 0000000..5b1734f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-mf4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf4_t,
+  vuint64m2_t,
+  __riscv_vle8_v_u8mf4,
+  __riscv_vzext_vf8_u64m2,
+  __riscv_vse64_v_u64m2,
+  vzext_vf,
+  LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vzext\.vf8\s+v0,v7([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf8\s+v8,v15} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf8\s+v16,v23} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf8\s+v24,v31} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-mf8.c
new file mode 100644 (file)
index 0000000..606af25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf8-u8-mf8.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf8_t,
+  vuint64m1_t,
+  __riscv_vle8_v_u8mf8,
+  __riscv_vzext_vf8_u64m1,
+  __riscv_vse64_v_u64m1,
+  vzext_vf,
+  LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vzext\.vf8\s+v0,v7([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf8\s+v8,v15} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf8\s+v16,v23} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf8\s+v24,v31} } } */