]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
5.10-stable patches
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 12 Oct 2023 18:05:19 +0000 (20:05 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 12 Oct 2023 18:05:19 +0000 (20:05 +0200)
added patches:
asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch

queue-5.10/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch [new file with mode: 0644]
queue-5.10/series

diff --git a/queue-5.10/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch b/queue-5.10/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch
new file mode 100644 (file)
index 0000000..5d67965
--- /dev/null
@@ -0,0 +1,53 @@
+From 197c53c8ecb34f2cd5922f4bdcffa8f701a134eb Mon Sep 17 00:00:00 2001
+From: Shengjiu Wang <shengjiu.wang@nxp.com>
+Date: Tue, 19 Sep 2023 17:42:13 +0800
+Subject: ASoC: fsl_sai: Don't disable bitclock for i.MX8MP
+
+From: Shengjiu Wang <shengjiu.wang@nxp.com>
+
+commit 197c53c8ecb34f2cd5922f4bdcffa8f701a134eb upstream.
+
+On i.MX8MP, the BCE and TERE bit are binding with mclk
+enablement, if BCE and TERE are cleared the MCLK also be
+disabled on output pin, that cause the external codec (wm8960)
+in wrong state.
+
+Codec (wm8960) is using the mclk to generate PLL clock,
+if mclk is disabled before disabling PLL, the codec (wm8960)
+won't generate bclk and frameclk when sysclk switch to
+MCLK source in next test case.
+
+The test case:
+$aplay -r44100 test1.wav (PLL source)
+$aplay -r48000 test2.wav (MCLK source)
+aplay: pcm_write:2127: write error: Input/output error
+
+Fixes: 269f399dc19f ("ASoC: fsl_sai: Disable bit clock with transmitter")
+Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
+Link: https://lore.kernel.org/r/1695116533-23287-1-git-send-email-shengjiu.wang@nxp.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ sound/soc/fsl/fsl_sai.c |    9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+--- a/sound/soc/fsl/fsl_sai.c
++++ b/sound/soc/fsl/fsl_sai.c
+@@ -549,10 +549,15 @@ static void fsl_sai_config_disable(struc
+ {
+       unsigned int ofs = sai->soc_data->reg_offset;
+       bool tx = dir == TX;
+-      u32 xcsr, count = 100;
++      u32 xcsr, count = 100, mask;
++
++      if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
++              mask = FSL_SAI_CSR_TERE;
++      else
++              mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE;
+       regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
+-                         FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE, 0);
++                         mask, 0);
+       /* TERE will remain set till the end of current frame */
+       do {
index 8a2b93e9b4831ac59041f0e87719d669bb2d8bae..ed20dc12ff9ee53190885c21359609fbaad50d8a 100644 (file)
@@ -7,3 +7,4 @@ lib-test_meminit-fix-off-by-one-error-in-test_pages.patch
 hid-logitech-hidpp-fix-kernel-crash-on-receiver-usb-disconnect.patch
 quota-fix-slow-quotaoff.patch
 net-prevent-address-rewrite-in-kernel_bind.patch
+asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch