tty: serial: imx: keep dma request disabled before dma transfer setup

Since sdma hardware configure postpone to transfer phase, have to
disable dma request before dma transfer setup because there is a
hardware limitation on sdma event enable(ENBLn) as below.

Refer SDMA 2.6.28 Channel Enable RAM (SDMAARMx_CHNENBLn) section:
"It is thus essential for the Arm platform to program them before any
DMA request is triggered to the SDMA, otherwise an unpredictable
combination of channels may be started."

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Link: https://patch.msgid.link/20260312094526.297348-1-sherry.sun@nxp.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index c488e5d372ffd30611b02550c3aadfb57383b065..251a50c8aa387213adf2794a969e2935be40c692 100644 (file)
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -1442,9 +1442,9 @@ static void imx_uart_enable_dma(struct imx_port *sport)
 
        imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
 
-       /* set UCR1 */
+       /* set UCR1 except TXDMAEN which would be enabled in imx_uart_dma_tx */
        ucr1 = imx_uart_readl(sport, UCR1);
-       ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
+       ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
        imx_uart_writel(sport, ucr1, UCR1);
 
        sport->dma_is_enabled = 1;
@@ -1567,8 +1567,9 @@ static int imx_uart_startup(struct uart_port *port)
        imx_uart_enable_ms(&sport->port);
 
        if (dma_is_inited) {
-               imx_uart_enable_dma(sport);
+               /* Note: enable dma request after transfer start! */
                imx_uart_start_rx_dma(sport);
+               imx_uart_enable_dma(sport);
        } else {
                ucr1 = imx_uart_readl(sport, UCR1);
                ucr1 |= UCR1_RRDYEN;