--- /dev/null
+From 5c6c13cd1102caf92d006a3cf4591c0229019daf Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Tue, 11 Aug 2020 10:25:32 +0100
+Subject: drm/i915: Drop runtime-pm assert from vgpu io accessors
+
+From: Chris Wilson <chris@chris-wilson.co.uk>
+
+commit 5c6c13cd1102caf92d006a3cf4591c0229019daf upstream.
+
+The "mmio" writes into vgpu registers are simple memory traps from the
+guest into the host. We do not need to assert in the guest that the
+device is awake for the io as we do not write to the device itself.
+
+However, over time we have refactored all the mmio accessors with the
+result that the vgpu reuses the gen2 accessors and so inherits the
+assert for runtime-pm of the native device. The assert though has
+actually been there since commit 3be0bf5acca6 ("drm/i915: Create vGPU
+specific MMIO operations to reduce traps").
+
+References: 3be0bf5acca6 ("drm/i915: Create vGPU specific MMIO operations to reduce traps")
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Yan Zhao <yan.y.zhao@intel.com>
+Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
+Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
+Cc: stable@vger.kernel.org
+Link: https://patchwork.freedesktop.org/patch/msgid/20200811092532.13753-1-chris@chris-wilson.co.uk
+(cherry picked from commit 0e65ce24a33c1d37da4bf43c34e080334ec6cb60)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_uncore.c | 27 ++++++++++++++++++++++++++-
+ 1 file changed, 26 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/intel_uncore.c
++++ b/drivers/gpu/drm/i915/intel_uncore.c
+@@ -1209,6 +1209,18 @@ unclaimed_reg_debug(struct intel_uncore
+ spin_unlock(&uncore->debug->lock);
+ }
+
++#define __vgpu_read(x) \
++static u##x \
++vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
++ u##x val = __raw_uncore_read##x(uncore, reg); \
++ trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
++ return val; \
++}
++__vgpu_read(8)
++__vgpu_read(16)
++__vgpu_read(32)
++__vgpu_read(64)
++
+ #define GEN2_READ_HEADER(x) \
+ u##x val = 0; \
+ assert_rpm_wakelock_held(uncore->rpm);
+@@ -1414,6 +1426,16 @@ __gen_reg_write_funcs(gen8);
+ #undef GEN6_WRITE_FOOTER
+ #undef GEN6_WRITE_HEADER
+
++#define __vgpu_write(x) \
++static void \
++vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
++ trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
++ __raw_uncore_write##x(uncore, reg, val); \
++}
++__vgpu_write(8)
++__vgpu_write(16)
++__vgpu_write(32)
++
+ #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
+ do { \
+ (uncore)->funcs.mmio_writeb = x##_write8; \
+@@ -1735,7 +1757,10 @@ static void uncore_raw_init(struct intel
+ {
+ GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
+
+- if (IS_GEN(uncore->i915, 5)) {
++ if (intel_vgpu_active(uncore->i915)) {
++ ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
++ ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
++ } else if (IS_GEN(uncore->i915, 5)) {
+ ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
+ ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
+ } else {
--- /dev/null
+From 3da3c5c1c9825c24168f27b021339e90af37e969 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Mon, 19 Oct 2020 17:50:05 +0100
+Subject: drm/i915: Exclude low pages (128KiB) of stolen from use
+
+From: Chris Wilson <chris@chris-wilson.co.uk>
+
+commit 3da3c5c1c9825c24168f27b021339e90af37e969 upstream.
+
+The GPU is trashing the low pages of its reserved memory upon reset. If
+we are using this memory for ringbuffers, then we will dutiful resubmit
+the trashed rings after the reset causing further resets, and worse. We
+must exclude this range from our own use. The value of 128KiB was found
+by empirical measurement (and verified now with a selftest) on gen9.
+
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: stable@vger.kernel.org
+Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20201019165005.18128-2-chris@chris-wilson.co.uk
+(cherry picked from commit d3606757e611fbd48bb239e8c2fe9779b3f50035)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/Kconfig.debug | 1
+ drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 6
+ drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 2
+ drivers/gpu/drm/i915/gt/selftest_reset.c | 196 +++++++++++++++++++++++++++++
+ 4 files changed, 203 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/Kconfig.debug
++++ b/drivers/gpu/drm/i915/Kconfig.debug
+@@ -153,6 +153,7 @@ config DRM_I915_SELFTEST
+ select DRM_EXPORT_FOR_TESTS if m
+ select FAULT_INJECTION
+ select PRIME_NUMBERS
++ select CRC32
+ help
+ Choose this option to allow the driver to perform selftests upon
+ loading; also requires the i915.selftest=1 module parameter. To
+--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
++++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+@@ -53,8 +53,10 @@ int i915_gem_stolen_insert_node(struct d
+ struct drm_mm_node *node, u64 size,
+ unsigned alignment)
+ {
+- return i915_gem_stolen_insert_node_in_range(i915, node, size,
+- alignment, 0, U64_MAX);
++ return i915_gem_stolen_insert_node_in_range(i915, node,
++ size, alignment,
++ I915_GEM_STOLEN_BIAS,
++ U64_MAX);
+ }
+
+ void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
+--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.h
++++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.h
+@@ -30,4 +30,6 @@ i915_gem_object_create_stolen_for_preall
+ resource_size_t stolen_offset,
+ resource_size_t size);
+
++#define I915_GEM_STOLEN_BIAS SZ_128K
++
+ #endif /* __I915_GEM_STOLEN_H__ */
+--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
++++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
+@@ -3,9 +3,203 @@
+ * Copyright © 2018 Intel Corporation
+ */
+
++#include <linux/crc32.h>
++
++#include "gem/i915_gem_stolen.h"
++
++#include "i915_memcpy.h"
+ #include "i915_selftest.h"
+ #include "selftests/igt_reset.h"
+ #include "selftests/igt_atomic.h"
++#include "selftests/igt_spinner.h"
++
++static int
++__igt_reset_stolen(struct intel_gt *gt,
++ intel_engine_mask_t mask,
++ const char *msg)
++{
++ struct i915_ggtt *ggtt = >->i915->ggtt;
++ const struct resource *dsm = >->i915->dsm;
++ resource_size_t num_pages, page;
++ struct intel_engine_cs *engine;
++ intel_wakeref_t wakeref;
++ enum intel_engine_id id;
++ struct igt_spinner spin;
++ long max, count;
++ void *tmp;
++ u32 *crc;
++ int err;
++
++ if (!drm_mm_node_allocated(&ggtt->error_capture))
++ return 0;
++
++ num_pages = resource_size(dsm) >> PAGE_SHIFT;
++ if (!num_pages)
++ return 0;
++
++ crc = kmalloc_array(num_pages, sizeof(u32), GFP_KERNEL);
++ if (!crc)
++ return -ENOMEM;
++
++ tmp = kmalloc(PAGE_SIZE, GFP_KERNEL);
++ if (!tmp) {
++ err = -ENOMEM;
++ goto err_crc;
++ }
++
++ igt_global_reset_lock(gt);
++ wakeref = intel_runtime_pm_get(gt->uncore->rpm);
++
++ err = igt_spinner_init(&spin, gt);
++ if (err)
++ goto err_lock;
++
++ for_each_engine(engine, gt, id) {
++ struct intel_context *ce;
++ struct i915_request *rq;
++
++ if (!(mask & engine->mask))
++ continue;
++
++ if (!intel_engine_can_store_dword(engine))
++ continue;
++
++ ce = intel_context_create(engine);
++ if (IS_ERR(ce)) {
++ err = PTR_ERR(ce);
++ goto err_spin;
++ }
++ rq = igt_spinner_create_request(&spin, ce, MI_ARB_CHECK);
++ intel_context_put(ce);
++ if (IS_ERR(rq)) {
++ err = PTR_ERR(rq);
++ goto err_spin;
++ }
++ i915_request_add(rq);
++ }
++
++ for (page = 0; page < num_pages; page++) {
++ dma_addr_t dma = (dma_addr_t)dsm->start + (page << PAGE_SHIFT);
++ void __iomem *s;
++ void *in;
++
++ ggtt->vm.insert_page(&ggtt->vm, dma,
++ ggtt->error_capture.start,
++ I915_CACHE_NONE, 0);
++ mb();
++
++ s = io_mapping_map_wc(&ggtt->iomap,
++ ggtt->error_capture.start,
++ PAGE_SIZE);
++
++ if (!__drm_mm_interval_first(>->i915->mm.stolen,
++ page << PAGE_SHIFT,
++ ((page + 1) << PAGE_SHIFT) - 1))
++ memset32(s, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
++
++ in = s;
++ if (i915_memcpy_from_wc(tmp, s, PAGE_SIZE))
++ in = tmp;
++ crc[page] = crc32_le(0, in, PAGE_SIZE);
++
++ io_mapping_unmap(s);
++ }
++ mb();
++ ggtt->vm.clear_range(&ggtt->vm, ggtt->error_capture.start, PAGE_SIZE);
++
++ if (mask == ALL_ENGINES) {
++ intel_gt_reset(gt, mask, NULL);
++ } else {
++ for_each_engine(engine, gt, id) {
++ if (mask & engine->mask)
++ intel_engine_reset(engine, NULL);
++ }
++ }
++
++ max = -1;
++ count = 0;
++ for (page = 0; page < num_pages; page++) {
++ dma_addr_t dma = (dma_addr_t)dsm->start + (page << PAGE_SHIFT);
++ void __iomem *s;
++ void *in;
++ u32 x;
++
++ ggtt->vm.insert_page(&ggtt->vm, dma,
++ ggtt->error_capture.start,
++ I915_CACHE_NONE, 0);
++ mb();
++
++ s = io_mapping_map_wc(&ggtt->iomap,
++ ggtt->error_capture.start,
++ PAGE_SIZE);
++
++ in = s;
++ if (i915_memcpy_from_wc(tmp, s, PAGE_SIZE))
++ in = tmp;
++ x = crc32_le(0, in, PAGE_SIZE);
++
++ if (x != crc[page] &&
++ !__drm_mm_interval_first(>->i915->mm.stolen,
++ page << PAGE_SHIFT,
++ ((page + 1) << PAGE_SHIFT) - 1)) {
++ pr_debug("unused stolen page %pa modified by GPU reset\n",
++ &page);
++ if (count++ == 0)
++ igt_hexdump(in, PAGE_SIZE);
++ max = page;
++ }
++
++ io_mapping_unmap(s);
++ }
++ mb();
++ ggtt->vm.clear_range(&ggtt->vm, ggtt->error_capture.start, PAGE_SIZE);
++
++ if (count > 0) {
++ pr_info("%s reset clobbered %ld pages of stolen, last clobber at page %ld\n",
++ msg, count, max);
++ }
++ if (max >= I915_GEM_STOLEN_BIAS >> PAGE_SHIFT) {
++ pr_err("%s reset clobbered unreserved area [above %x] of stolen; may cause severe faults\n",
++ msg, I915_GEM_STOLEN_BIAS);
++ err = -EINVAL;
++ }
++
++err_spin:
++ igt_spinner_fini(&spin);
++
++err_lock:
++ intel_runtime_pm_put(gt->uncore->rpm, wakeref);
++ igt_global_reset_unlock(gt);
++
++ kfree(tmp);
++err_crc:
++ kfree(crc);
++ return err;
++}
++
++static int igt_reset_device_stolen(void *arg)
++{
++ return __igt_reset_stolen(arg, ALL_ENGINES, "device");
++}
++
++static int igt_reset_engines_stolen(void *arg)
++{
++ struct intel_gt *gt = arg;
++ struct intel_engine_cs *engine;
++ enum intel_engine_id id;
++ int err;
++
++ if (!intel_has_reset_engine(gt))
++ return 0;
++
++ for_each_engine(engine, gt, id) {
++ err = __igt_reset_stolen(gt, engine->mask, engine->name);
++ if (err)
++ return err;
++ }
++
++ return 0;
++}
+
+ static int igt_global_reset(void *arg)
+ {
+@@ -164,6 +358,8 @@ int intel_reset_live_selftests(struct dr
+ {
+ static const struct i915_subtest tests[] = {
+ SUBTEST(igt_global_reset), /* attempt to recover GPU first */
++ SUBTEST(igt_reset_device_stolen),
++ SUBTEST(igt_reset_engines_stolen),
+ SUBTEST(igt_wedged_reset),
+ SUBTEST(igt_atomic_reset),
+ SUBTEST(igt_atomic_engine_reset),
--- /dev/null
+From 9b99e5ba3e5d68039bd6b657e4bbe520a3521f4c Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Thu, 15 Oct 2020 20:50:23 +0100
+Subject: drm/i915/gt: Delay execlist processing for tgl
+
+From: Chris Wilson <chris@chris-wilson.co.uk>
+
+commit 9b99e5ba3e5d68039bd6b657e4bbe520a3521f4c upstream.
+
+When running gem_exec_nop, it floods the system with many requests (with
+the goal of userspace submitting faster than the HW can process a single
+empty batch). This causes the driver to continually resubmit new
+requests onto the end of an active context, a flood of lite-restore
+preemptions. If we time this just right, Tigerlake hangs.
+
+Inserting a small delay between the processing of CS events and
+submitting the next context, prevents the hang. Naturally it does not
+occur with debugging enabled. The suspicion then is that this is related
+to the issues with the CS event buffer, and inserting an mmio read of
+the CS pointer status appears to be very successful in preventing the
+hang. Other registers, or uncached reads, or plain mb, do not prevent
+the hang, suggesting that register is key -- but that the hang can be
+prevented by a simple udelay, suggests it is just a timing issue like
+that encountered by commit 233c1ae3c83f ("drm/i915/gt: Wait for CSB
+entries on Tigerlake"). Also note that the hang is not prevented by
+applying CTX_DESC_FORCE_RESTORE, or by inserting a delay on the GPU
+between requests.
+
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Cc: Bruce Chang <yu.bruce.chang@intel.com>
+Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Cc: stable@vger.kernel.org
+Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20201015195023.32346-1-chris@chris-wilson.co.uk
+(cherry picked from commit 6ca7217dffaf1abba91558e67a2efb655ac91405)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
++++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
+@@ -2661,6 +2661,9 @@ static void process_csb(struct intel_eng
+ smp_wmb(); /* complete the seqlock */
+ WRITE_ONCE(execlists->active, execlists->inflight);
+
++ /* XXX Magic delay for tgl */
++ ENGINE_POSTING_READ(engine, RING_CONTEXT_STATUS_PTR);
++
+ WRITE_ONCE(execlists->pending[0], NULL);
+ } else {
+ if (GEM_WARN_ON(!*execlists->active)) {
--- /dev/null
+From 849c0fe9e831dcebea1b46e2237e13f274a8756a Mon Sep 17 00:00:00 2001
+From: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
+Date: Wed, 29 Jul 2020 15:55:39 +0530
+Subject: drm/i915/gt: Initialize reserved and unspecified MOCS indices
+
+From: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
+
+commit 849c0fe9e831dcebea1b46e2237e13f274a8756a upstream.
+
+In order to avoid functional breakage of mis-programmed applications that
+have grown to depend on unused MOCS entries, we are programming
+those entries to be equal to fully cached ("L3 + LLC") entry.
+
+These reserved and unspecified entries should not be used as they may be
+changed to less performant variants with better coherency in the future
+if more entries are needed.
+
+v2: As suggested by Lucas De Marchi to utilise __init_mocs_table for
+programming default value, setting I915_MOCS_PTE index of tgl_mocs_table
+with desired value.
+
+Cc: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Lucas De Marchi <lucas.demarchi@intel.com>
+Cc: Tomasz Lis <tomasz.lis@intel.com>
+Cc: Matt Roper <matthew.d.roper@intel.com>
+Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Cc: Francisco Jerez <currojerez@riseup.net>
+Cc: Mathew Alwin <alwin.mathew@intel.com>
+Cc: Mcguire Russell W <russell.w.mcguire@intel.com>
+Cc: Spruit Neil R <neil.r.spruit@intel.com>
+Cc: Zhou Cheng <cheng.zhou@intel.com>
+Cc: Benemelis Mike G <mike.g.benemelis@intel.com>
+
+Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
+Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Link: https://patchwork.freedesktop.org/patch/msgid/20200729102539.134731-2-ayaz.siddiqui@intel.com
+Cc: stable@vger.kernel.org
+(cherry picked from commit 4d8a5cfe3b131f60903949f998c5961cc922e0b0)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/gt/intel_mocs.c | 16 +++++++++++-----
+ 1 file changed, 11 insertions(+), 5 deletions(-)
+
+--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
++++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
+@@ -234,11 +234,17 @@ static const struct drm_i915_mocs_entry
+ L3_1_UC)
+
+ static const struct drm_i915_mocs_entry tgl_mocs_table[] = {
+- /* Base - Error (Reserved for Non-Use) */
+- MOCS_ENTRY(0, 0x0, 0x0),
+- /* Base - Reserved */
+- MOCS_ENTRY(1, 0x0, 0x0),
+-
++ /*
++ * NOTE:
++ * Reserved and unspecified MOCS indices have been set to (L3 + LCC).
++ * These reserved entries should never be used, they may be changed
++ * to low performant variants with better coherency in the future if
++ * more entries are needed. We are programming index I915_MOCS_PTE(1)
++ * only, __init_mocs_table() take care to program unused index with
++ * this entry.
++ */
++ MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
++ L3_3_WB),
+ GEN11_MOCS_ENTRIES,
+
+ /* Implicitly enable L1 - HDC:L1 + L3 + LLC */
--- /dev/null
+From 64402570e12f7b63ab33fc4640d3709c9ce2b380 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Fri, 2 Oct 2020 09:34:25 +0100
+Subject: drm/i915/gt: Undo forced context restores after trivial preemptions
+
+From: Chris Wilson <chris@chris-wilson.co.uk>
+
+commit 64402570e12f7b63ab33fc4640d3709c9ce2b380 upstream.
+
+We may try to preempt the currently executing request, only to find that
+after unravelling all the dependencies that the original executing
+context is still the earliest in the topological sort and re-submitted
+back to HW (if we do detect some change in the ELSP that requires
+re-submission). However, due to the way we check for wrap-around during
+the unravelling, we mark any context that has been submitted just once
+(i.e. with the rq->wa_tail set, but the ring->tail earlier) as
+potentially wrapping and requiring a forced restore on resubmission.
+This was expected to be not a problem, as it was anticipated that most
+unwinding for preemption would result in a context switch and the few
+that did not would be lost in the noise. It did not take long for
+someone to find one particular workload where the cost of those extra
+context restores was measurable.
+
+However, since we know the wa_tail is of fixed size, and we know that a
+request must be larger than the wa_tail itself, we can safely maintain
+the check for request wrapping and check against a slightly future point
+in the ring that includes an expected wa_tail. (That is if the
+ring->tail is already set to rq->wa_tail, including another 8 bytes in
+the check does not invalidate the incremental wrap detection.)
+
+Fixes: 8ab3a3812aa9 ("drm/i915/gt: Incrementally check for rewinding")
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Cc: Bruce Chang <yu.bruce.chang@intel.com>
+Cc: Ramalingam C <ramalingam.c@intel.com>
+Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Cc: <stable@vger.kernel.org> # v5.4+
+Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20201002083425.4605-1-chris@chris-wilson.co.uk
+(cherry picked from commit bb65548e3c6e299175a9e8c3e24b2b9577656a5d)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/gt/intel_lrc.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
++++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
+@@ -1139,9 +1139,8 @@ __unwind_incomplete_requests(struct inte
+
+ /* Check in case we rollback so far we wrap [size/2] */
+ if (intel_ring_direction(rq->ring,
+- intel_ring_wrap(rq->ring,
+- rq->tail),
+- rq->ring->tail) > 0)
++ rq->tail,
++ rq->ring->tail + 8) > 0)
+ rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE;
+
+ active = rq;
--- /dev/null
+From 1664ffee760a5d98952318fdd9b198fae396d660 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Thu, 15 Oct 2020 13:21:35 +0100
+Subject: drm/i915: Mark ininitial fb obj as WT on eLLC machines to avoid rcu lockup during fbdev init
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 1664ffee760a5d98952318fdd9b198fae396d660 upstream.
+
+Currently we leave the cache_level of the initial fb obj
+set to NONE. This means on eLLC machines the first pin_to_display()
+will try to switch it to WT which requires a vma unbind+bind.
+If that happens during the fbdev initialization rcu does not
+seem operational which causes the unbind to get stuck. To
+most appearances this looks like a dead machine on boot.
+
+Avoid the unbind by already marking the object cache_level
+as WT when creating it. We still do an excplicit ggtt pin
+which will rewrite the PTEs anyway, so they will match whatever
+cache level we set.
+
+Cc: <stable@vger.kernel.org> # v5.7+
+Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
+Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2381
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Link: https://patchwork.freedesktop.org/patch/msgid/20201007120329.17076-1-ville.syrjala@linux.intel.com
+Link: https://patchwork.freedesktop.org/patch/msgid/20201015122138.30161-1-chris@chris-wilson.co.uk
+(cherry picked from commit d46b60a2e8d246f1f0faa38e52f4f5a73858c338)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/gpu/drm/i915/display/intel_display.c
++++ b/drivers/gpu/drm/i915/display/intel_display.c
+@@ -3432,6 +3432,14 @@ initial_plane_vma(struct drm_i915_privat
+ if (IS_ERR(obj))
+ return NULL;
+
++ /*
++ * Mark it WT ahead of time to avoid changing the
++ * cache_level during fbdev initialization. The
++ * unbind there would get stuck waiting for rcu.
++ */
++ i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
++ I915_CACHE_WT : I915_CACHE_NONE);
++
+ switch (plane_config->tiling) {
+ case I915_TILING_NONE:
+ break;
--- /dev/null
+From 61334ed227a5852100115180f5535b1396ed5227 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Tue, 20 Oct 2020 22:43:29 +0300
+Subject: drm/i915: Reject 90/270 degree rotated initial fbs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 61334ed227a5852100115180f5535b1396ed5227 upstream.
+
+We don't currently handle the initial fb readout correctly
+for 90/270 degree rotated scanout. Reject it.
+
+Cc: stable@vger.kernel.org
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20201020194330.28568-1-ville.syrjala@linux.intel.com
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+(cherry picked from commit a40a8305a732f4ecc2186ac7ca132ba062ed770d)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/display/intel_display.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/gpu/drm/i915/display/intel_display.c
++++ b/drivers/gpu/drm/i915/display/intel_display.c
+@@ -10589,6 +10589,10 @@ skl_get_initial_plane_config(struct inte
+ val & PLANE_CTL_FLIP_HORIZONTAL)
+ plane_config->rotation |= DRM_MODE_REFLECT_X;
+
++ /* 90/270 degree rotation would require extra work */
++ if (drm_rotation_90_or_270(plane_config->rotation))
++ goto error;
++
+ base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
+ plane_config->base = base;
+
--- /dev/null
+From 5cbd7685b22823ebf432ec71eac1691b71c41037 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Wed, 21 Oct 2020 16:14:39 +0300
+Subject: drm/i915: Restore ILK-M RPS support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 5cbd7685b22823ebf432ec71eac1691b71c41037 upstream.
+
+Restore RPS for ILK-M. We lost it when an extra HAS_RPS()
+check appeared in intel_rps_enable().
+
+Unfortunaltey this just makes the performance worse on my
+ILK because intel_ips insists on limiting the GPU freq to
+the minimum. If we don't do the RPS init then intel_ips will
+not limit the frequency for whatever reason. Either it can't
+get at some required information and thus makes wrong decisions,
+or we mess up some weights/etc. and cause it to make the wrong
+decisions when RPS init has been done, or the entire thing is
+just wrong. Would require a bunch of reverse engineering to
+figure out what's going on.
+
+Cc: stable@vger.kernel.org
+Cc: Chris Wilson <chris@chris-wilson.co.uk>
+Fixes: 9c878557b1eb ("drm/i915/gt: Use the RPM config register to determine clk frequencies")
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20201021131443.25616-1-ville.syrjala@linux.intel.com
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+(cherry picked from commit 2bf06370bcfb0dea5655e9a5ad460c7f7dca7739)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_pci.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/gpu/drm/i915/i915_pci.c
++++ b/drivers/gpu/drm/i915/i915_pci.c
+@@ -389,6 +389,7 @@ static const struct intel_device_info il
+ GEN5_FEATURES,
+ PLATFORM(INTEL_IRONLAKE),
+ .is_mobile = 1,
++ .has_rps = true,
+ .display.has_fbc = 1,
+ };
+
--- /dev/null
+From db9bc2d35f49fed248296d3216597b078c0bab37 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Fri, 16 Oct 2020 10:25:27 +0100
+Subject: drm/i915: Use the active reference on the vma while capturing
+
+From: Chris Wilson <chris@chris-wilson.co.uk>
+
+commit db9bc2d35f49fed248296d3216597b078c0bab37 upstream.
+
+During error capture, we need to take a reference to the vma from before
+the reset in order to catpure the contents of the vma later. Currently
+we are using both an active reference and a kref, but due to nature of
+the i915_vma reference handling, that kref is on the vma->obj and not
+the vma itself. This means the vma may be destroyed as soon as it is
+idle, that is in between the i915_active_release(&vma->active) and the
+i915_vma_put(vma):
+
+<3> [197.866181] BUG: KASAN: use-after-free in intel_engine_coredump_add_vma+0x36c/0x4a0 [i915]
+<3> [197.866339] Read of size 8 at addr ffff8881258cb800 by task gem_exec_captur/1041
+<3> [197.866467]
+<4> [197.866512] CPU: 2 PID: 1041 Comm: gem_exec_captur Not tainted 5.9.0-g5e4234f97efba-kasan_200+ #1
+<4> [197.866521] Hardware name: Intel Corp. Broxton P/Apollolake RVP1A, BIOS APLKRVPA.X64.0150.B11.1608081044 08/08/2016
+<4> [197.866530] Call Trace:
+<4> [197.866549] dump_stack+0x99/0xd0
+<4> [197.866760] ? intel_engine_coredump_add_vma+0x36c/0x4a0 [i915]
+<4> [197.866783] print_address_description.constprop.8+0x3e/0x60
+<4> [197.866797] ? kmsg_dump_rewind_nolock+0xd4/0xd4
+<4> [197.866819] ? lockdep_hardirqs_off+0xd4/0x120
+<4> [197.867037] ? intel_engine_coredump_add_vma+0x36c/0x4a0 [i915]
+<4> [197.867249] ? intel_engine_coredump_add_vma+0x36c/0x4a0 [i915]
+<4> [197.867270] kasan_report.cold.10+0x1f/0x37
+<4> [197.867492] ? intel_engine_coredump_add_vma+0x36c/0x4a0 [i915]
+<4> [197.867710] intel_engine_coredump_add_vma+0x36c/0x4a0 [i915]
+<4> [197.867949] i915_gpu_coredump.part.29+0x150/0x7b0 [i915]
+<4> [197.868186] i915_capture_error_state+0x5e/0xc0 [i915]
+<4> [197.868396] intel_gt_handle_error+0x6eb/0xa20 [i915]
+<4> [197.868624] ? intel_gt_reset_global+0x370/0x370 [i915]
+<4> [197.868644] ? check_flags+0x50/0x50
+<4> [197.868662] ? __lock_acquire+0xd59/0x6b00
+<4> [197.868678] ? register_lock_class+0x1ad0/0x1ad0
+<4> [197.868944] i915_wedged_set+0xcf/0x1b0 [i915]
+<4> [197.869147] ? i915_wedged_get+0x90/0x90 [i915]
+<4> [197.869371] ? i915_wedged_get+0x90/0x90 [i915]
+<4> [197.869398] simple_attr_write+0x153/0x1c0
+<4> [197.869428] full_proxy_write+0xee/0x180
+<4> [197.869442] ? __sb_start_write+0x1f3/0x310
+<4> [197.869465] vfs_write+0x1a3/0x640
+<4> [197.869492] ksys_write+0xec/0x1c0
+<4> [197.869507] ? __ia32_sys_read+0xa0/0xa0
+<4> [197.869525] ? lockdep_hardirqs_on_prepare+0x32b/0x4e0
+<4> [197.869541] ? syscall_enter_from_user_mode+0x1c/0x50
+<4> [197.869566] do_syscall_64+0x33/0x80
+<4> [197.869579] entry_SYSCALL_64_after_hwframe+0x44/0xa9
+<4> [197.869590] RIP: 0033:0x7fd8b7aee281
+<4> [197.869604] Code: c3 0f 1f 84 00 00 00 00 00 48 8b 05 59 8d 20 00 c3 0f 1f 84 00 00 00 00 00 8b 05 8a d1 20 00 85 c0 75 16 b8 01 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 57 f3 c3 0f 1f 44 00 00 41 54 55 49 89 d4 53
+<4> [197.869613] RSP: 002b:00007ffea3b72008 EFLAGS: 00000246 ORIG_RAX: 0000000000000001
+<4> [197.869625] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007fd8b7aee281
+<4> [197.869633] RDX: 0000000000000002 RSI: 00007fd8b81a82e7 RDI: 000000000000000d
+<4> [197.869641] RBP: 0000000000000002 R08: 0000000000000000 R09: 0000000000000034
+<4> [197.869650] R10: 0000000000000000 R11: 0000000000000246 R12: 00007fd8b81a82e7
+<4> [197.869658] R13: 000000000000000d R14: 0000000000000000 R15: 0000000000000000
+<3> [197.869707]
+<3> [197.869757] Allocated by task 1041:
+<4> [197.869833] kasan_save_stack+0x19/0x40
+<4> [197.869843] __kasan_kmalloc.constprop.5+0xc1/0xd0
+<4> [197.869853] kmem_cache_alloc+0x106/0x8e0
+<4> [197.870059] i915_vma_instance+0x212/0x1930 [i915]
+<4> [197.870270] eb_lookup_vmas+0xe06/0x1d10 [i915]
+<4> [197.870475] i915_gem_do_execbuffer+0x131d/0x4080 [i915]
+<4> [197.870682] i915_gem_execbuffer2_ioctl+0x103/0x5d0 [i915]
+<4> [197.870701] drm_ioctl_kernel+0x1d2/0x270
+<4> [197.870710] drm_ioctl+0x40d/0x85c
+<4> [197.870721] __x64_sys_ioctl+0x10d/0x170
+<4> [197.870731] do_syscall_64+0x33/0x80
+<4> [197.870740] entry_SYSCALL_64_after_hwframe+0x44/0xa9
+<3> [197.870748]
+<3> [197.870798] Freed by task 22:
+<4> [197.870865] kasan_save_stack+0x19/0x40
+<4> [197.870875] kasan_set_track+0x1c/0x30
+<4> [197.870884] kasan_set_free_info+0x1b/0x30
+<4> [197.870894] __kasan_slab_free+0x111/0x160
+<4> [197.870903] kmem_cache_free+0xcd/0x710
+<4> [197.871109] i915_vma_parked+0x618/0x800 [i915]
+<4> [197.871307] __gt_park+0xdb/0x1e0 [i915]
+<4> [197.871501] ____intel_wakeref_put_last+0xb1/0x190 [i915]
+<4> [197.871516] process_one_work+0x8dc/0x15d0
+<4> [197.871525] worker_thread+0x82/0xb30
+<4> [197.871535] kthread+0x36d/0x440
+<4> [197.871545] ret_from_fork+0x22/0x30
+<3> [197.871553]
+<3> [197.871602] The buggy address belongs to the object at ffff8881258cb740
+ which belongs to the cache i915_vma of size 968
+
+Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2553
+Fixes: 2850748ef876 ("drm/i915: Pull i915_vma_pin under the vm->mutex")
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
+Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Cc: <stable@vger.kernel.org> # v5.5+
+Reviewed-by: Matthew Auld <matthew.auld@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20201016092527.29039-1-chris@chris-wilson.co.uk
+(cherry picked from commit 178536b8292ecd118f59d2fac4509c7e70b99854)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_gpu_error.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_gpu_error.c
++++ b/drivers/gpu/drm/i915/i915_gpu_error.c
+@@ -1312,7 +1312,7 @@ capture_vma(struct intel_engine_capture_
+ }
+
+ strcpy(c->name, name);
+- c->vma = i915_vma_get(vma);
++ c->vma = vma; /* reference held while active */
+
+ c->next = next;
+ return c;
+@@ -1402,7 +1402,6 @@ intel_engine_coredump_add_vma(struct int
+ compress));
+
+ i915_active_release(&vma->active);
+- i915_vma_put(vma);
+
+ capture = this->next;
+ kfree(this);
--- /dev/null
+From dcd292c172493067a72672b245a3dd1bcf7268dd Mon Sep 17 00:00:00 2001
+From: Karol Herbst <kherbst@redhat.com>
+Date: Tue, 13 Oct 2020 14:01:26 +0200
+Subject: drm/nouveau/device: fix changing endianess code to work on older GPUs
+
+From: Karol Herbst <kherbst@redhat.com>
+
+commit dcd292c172493067a72672b245a3dd1bcf7268dd upstream.
+
+With this we try to detect if the endianess switch works and assume LE if
+not. Suggested by Ben.
+
+Fixes: 51c05340e407 ("drm/nouveau/device: detect if changing endianness failed")
+Signed-off-by: Karol Herbst <kherbst@redhat.com>
+Cc: <stable@vger.kernel.org> # v5.8+
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 39 ++++++++++++++--------
+ 1 file changed, 26 insertions(+), 13 deletions(-)
+
+--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
++++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+@@ -2924,17 +2924,34 @@ nvkm_device_del(struct nvkm_device **pde
+ }
+ }
+
++/* returns true if the GPU is in the CPU native byte order */
+ static inline bool
+ nvkm_device_endianness(struct nvkm_device *device)
+ {
+- u32 boot1 = nvkm_rd32(device, 0x000004) & 0x01000001;
+ #ifdef __BIG_ENDIAN
+- if (!boot1)
+- return false;
++ const bool big_endian = true;
+ #else
+- if (boot1)
+- return false;
++ const bool big_endian = false;
+ #endif
++
++ /* Read NV_PMC_BOOT_1, and assume non-functional endian switch if it
++ * doesn't contain the expected values.
++ */
++ u32 pmc_boot_1 = nvkm_rd32(device, 0x000004);
++ if (pmc_boot_1 && pmc_boot_1 != 0x01000001)
++ return !big_endian; /* Assume GPU is LE in this case. */
++
++ /* 0 means LE and 0x01000001 means BE GPU. Condition is true when
++ * GPU/CPU endianness don't match.
++ */
++ if (big_endian == !pmc_boot_1) {
++ nvkm_wr32(device, 0x000004, 0x01000001);
++ nvkm_rd32(device, 0x000000);
++ if (nvkm_rd32(device, 0x000004) != (big_endian ? 0x01000001 : 0x00000000))
++ return !big_endian; /* Assume GPU is LE on any unexpected read-back. */
++ }
++
++ /* CPU/GPU endianness should (hopefully) match. */
+ return true;
+ }
+
+@@ -2987,14 +3004,10 @@ nvkm_device_ctor(const struct nvkm_devic
+ if (detect) {
+ /* switch mmio to cpu's native endianness */
+ if (!nvkm_device_endianness(device)) {
+- nvkm_wr32(device, 0x000004, 0x01000001);
+- nvkm_rd32(device, 0x000000);
+- if (!nvkm_device_endianness(device)) {
+- nvdev_error(device,
+- "GPU not supported on big-endian\n");
+- ret = -ENOSYS;
+- goto done;
+- }
++ nvdev_error(device,
++ "Couldn't switch GPU to CPUs endianess\n");
++ ret = -ENOSYS;
++ goto done;
+ }
+
+ boot0 = nvkm_rd32(device, 0x000000);
--- /dev/null
+From 24d9422e26ea75118acf00172f83417c296f5b5f Mon Sep 17 00:00:00 2001
+From: Lyude Paul <lyude@redhat.com>
+Date: Fri, 4 Sep 2020 16:27:58 -0400
+Subject: drm/nouveau/kms/nv50-: Program notifier offset before requesting disp caps
+
+From: Lyude Paul <lyude@redhat.com>
+
+commit 24d9422e26ea75118acf00172f83417c296f5b5f upstream.
+
+Not entirely sure why this never came up when I originally tested this
+(maybe some BIOSes already have this setup?) but the ->caps_init vfunc
+appears to cause the display engine to throw an exception on driver
+init, at least on my ThinkPad P72:
+
+nouveau 0000:01:00.0: disp: chid 0 mthd 008c data 00000000 0000508c 0000102b
+
+This is magic nvidia speak for "You need to have the DMA notifier offset
+programmed before you can call NV507D_GET_CAPABILITIES." So, let's fix
+this by doing that, and also perform an update afterwards to prevent
+racing with the GPU when reading capabilities.
+
+v2:
+* Don't just program the DMA notifier offset, make sure to actually
+ perform an update
+v3:
+* Don't call UPDATE()
+* Actually read the correct notifier fields, as apparently the
+ CAPABILITIES_DONE field lives in a different location than the main
+ NV_DISP_CORE_NOTIFIER_1 field. As well, 907d+ use a different
+ CAPABILITIES_DONE field then pre-907d cards.
+v4:
+* Don't forget to check the return value of core507d_read_caps()
+v5:
+* Get rid of NV50_DISP_CAPS_NTFY[14], use NV50_DISP_CORE_NTFY
+* Disable notifier after calling GetCapabilities()
+
+Signed-off-by: Lyude Paul <lyude@redhat.com>
+Fixes: 4a2cb4181b07 ("drm/nouveau/kms/nv50-: Probe SOR and PIOR caps for DP interlacing support")
+Cc: <stable@vger.kernel.org> # v5.8+
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/nouveau/dispnv50/core.h | 2
+ drivers/gpu/drm/nouveau/dispnv50/core507d.c | 41 +++++++++++++++++++-
+ drivers/gpu/drm/nouveau/dispnv50/core907d.c | 36 +++++++++++++++++
+ drivers/gpu/drm/nouveau/dispnv50/core917d.c | 2
+ drivers/gpu/drm/nouveau/include/nvhw/class/cl507d.h | 5 +-
+ drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h | 4 +
+ 6 files changed, 85 insertions(+), 5 deletions(-)
+
+--- a/drivers/gpu/drm/nouveau/dispnv50/core.h
++++ b/drivers/gpu/drm/nouveau/dispnv50/core.h
+@@ -44,6 +44,7 @@ int core507d_new_(const struct nv50_core
+ struct nv50_core **);
+ int core507d_init(struct nv50_core *);
+ void core507d_ntfy_init(struct nouveau_bo *, u32);
++int core507d_read_caps(struct nv50_disp *disp);
+ int core507d_caps_init(struct nouveau_drm *, struct nv50_disp *);
+ int core507d_ntfy_wait_done(struct nouveau_bo *, u32, struct nvif_device *);
+ int core507d_update(struct nv50_core *, u32 *, bool);
+@@ -55,6 +56,7 @@ extern const struct nv50_outp_func pior5
+ int core827d_new(struct nouveau_drm *, s32, struct nv50_core **);
+
+ int core907d_new(struct nouveau_drm *, s32, struct nv50_core **);
++int core907d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp);
+ extern const struct nv50_outp_func dac907d;
+ extern const struct nv50_outp_func sor907d;
+
+--- a/drivers/gpu/drm/nouveau/dispnv50/core507d.c
++++ b/drivers/gpu/drm/nouveau/dispnv50/core507d.c
+@@ -78,19 +78,56 @@ core507d_ntfy_init(struct nouveau_bo *bo
+ }
+
+ int
+-core507d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp)
++core507d_read_caps(struct nv50_disp *disp)
+ {
+ struct nvif_push *push = disp->core->chan.push;
+ int ret;
+
+- if ((ret = PUSH_WAIT(push, 2)))
++ ret = PUSH_WAIT(push, 6);
++ if (ret)
+ return ret;
+
++ PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
++ NVDEF(NV507D, SET_NOTIFIER_CONTROL, MODE, WRITE) |
++ NVVAL(NV507D, SET_NOTIFIER_CONTROL, OFFSET, NV50_DISP_CORE_NTFY >> 2) |
++ NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE));
++
+ PUSH_MTHD(push, NV507D, GET_CAPABILITIES, 0x00000000);
++
++ PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
++ NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, DISABLE));
++
+ return PUSH_KICK(push);
+ }
+
+ int
++core507d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp)
++{
++ struct nv50_core *core = disp->core;
++ struct nouveau_bo *bo = disp->sync;
++ s64 time;
++ int ret;
++
++ NVBO_WR32(bo, NV50_DISP_CORE_NTFY, NV_DISP_CORE_NOTIFIER_1, CAPABILITIES_1,
++ NVDEF(NV_DISP_CORE_NOTIFIER_1, CAPABILITIES_1, DONE, FALSE));
++
++ ret = core507d_read_caps(disp);
++ if (ret < 0)
++ return ret;
++
++ time = nvif_msec(core->chan.base.device, 2000ULL,
++ if (NVBO_TD32(bo, NV50_DISP_CORE_NTFY,
++ NV_DISP_CORE_NOTIFIER_1, CAPABILITIES_1, DONE, ==, TRUE))
++ break;
++ usleep_range(1, 2);
++ );
++ if (time < 0)
++ NV_ERROR(drm, "core caps notifier timeout\n");
++
++ return 0;
++}
++
++int
+ core507d_init(struct nv50_core *core)
+ {
+ struct nvif_push *push = core->chan.push;
+--- a/drivers/gpu/drm/nouveau/dispnv50/core907d.c
++++ b/drivers/gpu/drm/nouveau/dispnv50/core907d.c
+@@ -22,11 +22,45 @@
+ #include "core.h"
+ #include "head.h"
+
++#include <nvif/push507c.h>
++#include <nvif/timer.h>
++
++#include <nvhw/class/cl907d.h>
++
++#include "nouveau_bo.h"
++
++int
++core907d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp)
++{
++ struct nv50_core *core = disp->core;
++ struct nouveau_bo *bo = disp->sync;
++ s64 time;
++ int ret;
++
++ NVBO_WR32(bo, NV50_DISP_CORE_NTFY, NV907D_CORE_NOTIFIER_3, CAPABILITIES_4,
++ NVDEF(NV907D_CORE_NOTIFIER_3, CAPABILITIES_4, DONE, FALSE));
++
++ ret = core507d_read_caps(disp);
++ if (ret < 0)
++ return ret;
++
++ time = nvif_msec(core->chan.base.device, 2000ULL,
++ if (NVBO_TD32(bo, NV50_DISP_CORE_NTFY,
++ NV907D_CORE_NOTIFIER_3, CAPABILITIES_4, DONE, ==, TRUE))
++ break;
++ usleep_range(1, 2);
++ );
++ if (time < 0)
++ NV_ERROR(drm, "core caps notifier timeout\n");
++
++ return 0;
++}
++
+ static const struct nv50_core_func
+ core907d = {
+ .init = core507d_init,
+ .ntfy_init = core507d_ntfy_init,
+- .caps_init = core507d_caps_init,
++ .caps_init = core907d_caps_init,
+ .ntfy_wait_done = core507d_ntfy_wait_done,
+ .update = core507d_update,
+ .head = &head907d,
+--- a/drivers/gpu/drm/nouveau/dispnv50/core917d.c
++++ b/drivers/gpu/drm/nouveau/dispnv50/core917d.c
+@@ -26,7 +26,7 @@ static const struct nv50_core_func
+ core917d = {
+ .init = core507d_init,
+ .ntfy_init = core507d_ntfy_init,
+- .caps_init = core507d_caps_init,
++ .caps_init = core907d_caps_init,
+ .ntfy_wait_done = core507d_ntfy_wait_done,
+ .update = core507d_update,
+ .head = &head917d,
+--- a/drivers/gpu/drm/nouveau/include/nvhw/class/cl507d.h
++++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl507d.h
+@@ -32,7 +32,10 @@
+ #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001
+ #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_R0 15:1
+ #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP 29:16
+-
++#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001
++#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0
++#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE 0x00000000
++#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE 0x00000001
+
+ // class methods
+ #define NV507D_UPDATE (0x00000080)
+--- a/drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h
++++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h
+@@ -24,6 +24,10 @@
+ #ifndef _cl907d_h_
+ #define _cl907d_h_
+
++#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
++#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
++#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
++#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
+ #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
+ #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
+ #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
drm-i915-cancel-outstanding-work-after-disabling-heartbeats-on-an-engine.patch
drm-i915-avoid-mixing-integer-types-during-batch-copies.patch
drm-i915-fix-tgl-dkl-phy-dp-vswing-handling.patch
+drm-i915-gt-initialize-reserved-and-unspecified-mocs-indices.patch
+drm-i915-gt-undo-forced-context-restores-after-trivial-preemptions.patch
+drm-i915-gt-delay-execlist-processing-for-tgl.patch
+drm-i915-drop-runtime-pm-assert-from-vgpu-io-accessors.patch
+drm-i915-exclude-low-pages-128kib-of-stolen-from-use.patch
+drm-i915-mark-ininitial-fb-obj-as-wt-on-ellc-machines-to-avoid-rcu-lockup-during-fbdev-init.patch
+drm-i915-use-the-active-reference-on-the-vma-while-capturing.patch
+drm-i915-reject-90-270-degree-rotated-initial-fbs.patch
+drm-i915-restore-ilk-m-rps-support.patch
+drm-nouveau-kms-nv50-program-notifier-offset-before-requesting-disp-caps.patch
+drm-nouveau-device-fix-changing-endianess-code-to-work-on-older-gpus.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
