]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
net: stmmac: use u8 for host_dma_width and similar struct members
authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Mon, 9 Mar 2026 09:39:39 +0000 (09:39 +0000)
committerJakub Kicinski <kuba@kernel.org>
Wed, 11 Mar 2026 02:54:07 +0000 (19:54 -0700)
We aren't going to see >= 256-bit address busses soon, so reduce
host_dma_width and associated other struct members that initialise
this from u32 to u8.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Acked-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com> # qcom-ethqos
Tested-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Link: https://patch.msgid.link/E1vzX5P-0000000CVsK-0iwX@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
include/linux/stmmac.h

index 9f5a15b81f8a01d2b3e6975361a437ab80a5d7e5..9d1bd72ffb730bb16b9c714bd8ad54f710f3ca44 100644 (file)
@@ -42,8 +42,8 @@
 struct imx_priv_data;
 
 struct imx_dwmac_ops {
-       u32 addr_width;
        u32 flags;
+       u8 addr_width;
        bool mac_rgmii_txclk_auto_adj;
 
        int (*fix_soc_reset)(struct stmmac_priv *priv);
index a139db6a8cbb3188b179648cd496cd718e90f1dd..30ae0dba7fffdb43a1518fb5eef285ad88c5b8af 100644 (file)
@@ -93,9 +93,9 @@ struct mediatek_dwmac_variant {
        const char * const *clk_list;
        int num_clks;
 
-       u32 dma_bit_mask;
        u32 rx_delay_max;
        u32 tx_delay_max;
+       u8 dma_bit_mask;
 };
 
 /* list of clocks required for mac */
@@ -268,9 +268,9 @@ static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
                .dwmac_set_delay = mt2712_set_delay,
                .clk_list = mt2712_dwmac_clk_l,
                .num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l),
-               .dma_bit_mask = 33,
                .rx_delay_max = 17600,
                .tx_delay_max = 17600,
+               .dma_bit_mask = 33,
 };
 
 static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat,
@@ -418,9 +418,9 @@ static const struct mediatek_dwmac_variant mt8195_gmac_variant = {
        .dwmac_set_delay = mt8195_set_delay,
        .clk_list = mt8195_dwmac_clk_l,
        .num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l),
-       .dma_bit_mask = 35,
        .rx_delay_max = 9280,
        .tx_delay_max = 9280,
+       .dma_bit_mask = 35,
 };
 
 static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
index 388e9fdeb86cda87517fbfefe09b9b96000b3cbe..3ccf20fdf52a8ec4649b43ade8ee7b85d613e1c5 100644 (file)
@@ -91,8 +91,8 @@ struct ethqos_emac_driver_data {
        unsigned int num_rgmii_por;
        bool rgmii_config_loopback_en;
        bool has_emac_ge_3;
+       u8 dma_addr_width;
        const char *link_clk_name;
-       u32 dma_addr_width;
        struct dwmac4_addrs dwmac4_addrs;
        bool needs_sgmii_loopback;
 };
index 03fd85060a736d2f734943f1b9bf5b213987d175..11886189bf510674b81b0623d6dd93eed853c9c5 100644 (file)
@@ -243,7 +243,7 @@ struct plat_stmmacenet_data {
        int unicast_filter_entries;
        int tx_fifo_size;
        int rx_fifo_size;
-       u32 host_dma_width;
+       u8 host_dma_width;
        u8 rx_queues_to_use;
        u8 tx_queues_to_use;
        u8 rx_sched_algorithm;