clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz

[ Upstream commit dafebd0f9a4f56b10d7fbda0bff1f540d16a2ea4 ]

PLL rate on RK356x is calculated through the simple formula:
((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)

The PLL rate setting for 78.75MHz seems to be copied from 96MHz
so this patch fixes it and configures it properly.

Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
Fixes: 842f4cb72639 ("clk: rockchip: Add more PLL rates for rk3568")
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20230614134750.1056293-1-a1ba.omarov@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index f85902e2590c7feaad6884dbf9d6400148676494..2f54f630c8b65c8f26b046a1fd23025a61637ff9 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -81,7 +81,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
        RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
        RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
        RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
-       RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
+       RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
        RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
        { /* sentinel */ },
 };