]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/xe/xe3p: Dump CSMQDEBUG register
authorWang Xin <x.wang@intel.com>
Fri, 17 Oct 2025 02:26:29 +0000 (19:26 -0700)
committerLucas De Marchi <lucas.demarchi@intel.com>
Fri, 17 Oct 2025 22:32:38 +0000 (15:32 -0700)
The CSMQDEBUG is useful for the development of MQ feature. Start dumping
the debug register.

Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Wang Xin <x.wang@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20251016-xe3p-v3-10-3dd173a3097a@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
drivers/gpu/drm/xe/regs/xe_engine_regs.h
drivers/gpu/drm/xe/xe_guc_capture.c

index 0c02d0fe553153f0f39c0db01e557d71914ba3c2..68172b0248a6e43c4c9f5cc9b22f438b45d11a65 100644 (file)
 #define   GFX_DISABLE_LEGACY_MODE              REG_BIT(3)
 #define   GFX_MSIX_INTERRUPT_ENABLE            REG_BIT(13)
 
+#define RING_CSMQDEBUG(base)                   XE_REG((base) + 0x2b0)
+
 #define RING_TIMESTAMP(base)                   XE_REG((base) + 0x358)
 
 #define RING_TIMESTAMP_UDW(base)               XE_REG((base) + 0x358 + 4)
index 8d1bfa2cdb151213c9b86782313266fc8239826a..0c1fbe97b8bf2ce4a1251d2cd6c434a6e332c914 100644 (file)
@@ -150,6 +150,9 @@ struct __guc_capture_parsed_output {
        { SFC_DONE(2),                  0,      0,      0,      0,      "SFC_DONE[2]"}, \
        { SFC_DONE(3),                  0,      0,      0,      0,      "SFC_DONE[3]"}
 
+#define XE3P_BASE_ENGINE_INSTANCE \
+       { RING_CSMQDEBUG(0),            REG_32BIT,      0,      0,      0,      "CSMQDEBUG"}
+
 /* XE_LP Global */
 static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
        COMMON_XELP_BASE_GLOBAL,
@@ -196,6 +199,12 @@ static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
        COMMON_BASE_ENGINE_INSTANCE,
 };
 
+/* Render / Compute Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = {
+       COMMON_BASE_ENGINE_INSTANCE,
+       XE3P_BASE_ENGINE_INSTANCE,
+};
+
 /*
  * Empty list to prevent warnings about unknown class/instance types
  * as not all class/instance types have entries on all platforms.
@@ -246,6 +255,21 @@ static const struct __guc_mmio_reg_descr_group xe_hpg_lists[] = {
        {}
 };
 
+ /* List of lists for Xe3p and beyond */
+static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
+       MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
+       MAKE_REGLIST(xe_hpg_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
+       MAKE_REGLIST(xe3p_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
+       MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
+       MAKE_REGLIST(xe_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
+       MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
+       MAKE_REGLIST(xe_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
+       MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
+       MAKE_REGLIST(xe_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
+       MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
+       MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
+       {}
+};
 static const char * const capture_list_type_names[] = {
        "Global",
        "Class",
@@ -293,7 +317,9 @@ guc_capture_remove_stale_matches_from_list(struct xe_guc_state_capture *gc,
 static const struct __guc_mmio_reg_descr_group *
 guc_capture_get_device_reglist(struct xe_device *xe)
 {
-       if (GRAPHICS_VERx100(xe) >= 1255)
+       if (GRAPHICS_VER(xe) >= 35)
+               return xe3p_lists;
+       else if (GRAPHICS_VERx100(xe) >= 1255)
                return xe_hpg_lists;
        else
                return xe_lp_lists;