arm64: dts: ti: k3-am69-sk: Switch to PCIe Multilink + USB configuration

The SERDES0 instance of SERDES on the AM69 SoC is a Cadence Torrent SERDES
and it has 4 lanes which are allocated in the following manner:
Lane0 and Lane1 to PCIe1
Lane2 to PCIe3
Lane3 to USB0

Until [0], the Cadence Torrent SERDES driver only supported configuring
the SERDES for a PCIe + USB configuration whereby all lanes of the
SERDES configured for PCIe will operate at the same speed. As a result,
PCIe1 and PCIe3 instances of PCIe will either fall down to a common
speed based on the PCIe peers that they are each connected to, or, the
PCIe link could fail to be setup.

Since [0] enables support for PCIe Multilink + USB configuration, it is
now possible for the SERDES lanes allocated to PCIe1 and PCIe3 to link up
and operate at different speeds. USB continues to remain functional.

Hence, update the 'serdes0' node as well as the 'pcie1_rc' and 'pcie3_rc'
nodes to switch to the PCIe Multilink + USB configuration that is now
supported by the Cadence Torrent SERDES driver.

[0]: commit 351e07e6b2ec ("phy: cadence-torrent: Add PCIe multilink + USB with same SSC register config for 100 MHz refclk")

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://patch.msgid.link/20250819105717.372893-1-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
index 612ac27643d2cee62a3414623d1cb19288c1c83f..f4f7b89bf0d22ce4cb4fd783870259c3d98aa458 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
@@ -1321,12 +1321,20 @@
 &serdes0 {
        status = "okay";
 
-       serdes0_pcie_link: phy@0 {
+       serdes0_pcie1_link: phy@0 {
                reg = <0>;
-               cdns,num-lanes = <3>;
+               cdns,num-lanes = <2>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_PCIE>;
-               resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>;
+               resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+       };
+
+       serdes0_pcie3_link: phy@2 {
+               reg = <2>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz0 3>;
        };
 
        serdes0_usb_link: phy@3 {
@@ -1364,7 +1372,7 @@
 &pcie1_rc {
        status = "okay";
        reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
-       phys = <&serdes0_pcie_link>;
+       phys = <&serdes0_pcie1_link>;
        phy-names = "pcie-phy";
        num-lanes = <2>;
 };
@@ -1372,7 +1380,7 @@
 &pcie3_rc {
        status = "okay";
        reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
-       phys = <&serdes0_pcie_link>;
+       phys = <&serdes0_pcie3_link>;
        phy-names = "pcie-phy";
        num-lanes = <1>;
 };