drm/i915: Don't pass the latency array to {skl,mtl}_read_wm_latency()

We always operate on i915->display.wm.skl_latency in
{skl,mtl}_read_wm_latency(). No real need for the caller
to have to pass that in explicitly.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250919193000.17665-5-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 2969cc58dabe903d1ae18e328e78a3b0b13eb0d0..43e481759e6e6855557435df181ce91da255389d 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3184,9 +3184,10 @@ static bool need_16gb_dimm_wa(struct intel_display *display)
 }
 
 static void
-adjust_wm_latency(struct intel_display *display,
-                 u16 wm[], int num_levels, int read_latency)
+adjust_wm_latency(struct intel_display *display, int read_latency)
 {
+       u16 *wm = display->wm.skl_latency;
+       int num_levels = display->wm.num_levels;
        int i, level;
 
        /*
@@ -3230,9 +3231,9 @@ adjust_wm_latency(struct intel_display *display,
                wm[0] += 1;
 }
 
-static void mtl_read_wm_latency(struct intel_display *display, u16 wm[])
+static void mtl_read_wm_latency(struct intel_display *display)
 {
-       int num_levels = display->wm.num_levels;
+       u16 *wm = display->wm.skl_latency;
        u32 val;
 
        val = intel_de_read(display, MTL_LATENCY_LP0_LP1);
@@ -3247,12 +3248,12 @@ static void mtl_read_wm_latency(struct intel_display *display, u16 wm[])
        wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
        wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
 
-       adjust_wm_latency(display, wm, num_levels, 6);
+       adjust_wm_latency(display, 6);
 }
 
-static void skl_read_wm_latency(struct intel_display *display, u16 wm[])
+static void skl_read_wm_latency(struct intel_display *display)
 {
-       int num_levels = display->wm.num_levels;
+       u16 *wm = display->wm.skl_latency;
        int read_latency = DISPLAY_VER(display) >= 12 ? 3 : 2;
        int mult = display->platform.dg2 ? 2 : 1;
        u32 val;
@@ -3284,7 +3285,7 @@ static void skl_read_wm_latency(struct intel_display *display, u16 wm[])
        wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult;
        wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult;
 
-       adjust_wm_latency(display, wm, num_levels, read_latency);
+       adjust_wm_latency(display, read_latency);
 }
 
 static void skl_setup_wm_latency(struct intel_display *display)
@@ -3295,9 +3296,9 @@ static void skl_setup_wm_latency(struct intel_display *display)
                display->wm.num_levels = 8;
 
        if (DISPLAY_VER(display) >= 14)
-               mtl_read_wm_latency(display, display->wm.skl_latency);
+               mtl_read_wm_latency(display);
        else
-               skl_read_wm_latency(display, display->wm.skl_latency);
+               skl_read_wm_latency(display);
 
        intel_print_wm_latency(display, "Gen9 Plane", display->wm.skl_latency);
 }