zynq-zed.dtb \
zynq-zybo.dtb \
zynq-microzed.dtb \
+ zynq-cc108.dtb \
zynq-picozed.dtb \
+ zynq-topic-miami.dtb \
+ zynq-topic-miamiplus.dtb \
zynq-zc770-xm010.dtb \
zynq-zc770-xm011.dtb \
zynq-zc770-xm012.dtb \
#define ARASAN_NAND_BASEADDR 0xFF100000
- #define ZYNQMP_SATA_BASEADDR 0xFD0C0000
-#define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000
-#define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000
--
#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
u32 check_val;
};
-
+static const int qspi0_pins[] = {
+ 1, 2, 3, 4, 5, 6
+};
+
+static const int qspi1_cs_pin[] = {
+ 0
+};
+
+static const int qspi1_pins[] = {
+ 9, 10, 11, 12, 13
+};
+
+static const int qspi0_dio_pins[] = {
+ 1, 2, 3, 6
+};
+
+static const int qspi1_cs_dio_pin[] = {
+ 0
+};
+
+static const int qspi1_dio_pins[] = {
+ 9, 10, 11
+};
+
static const int nand8_pins[] = {
0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
};
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
+#if defined(CONFIG_CMD_BOOTB)
+#include <asm/icap.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
+ int arch_fixup_fdt(void *blob)
+ {
+ return 0;
+ }
+
int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *images)
{
{
}
- #ifdef CONFIG_SCSI_AHCI_PLAT
- void scsi_init(void)
- {
- #if defined(CONFIG_SATA_CEVA)
- init_sata(0);
- #endif
- ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
- scsi_scan(1);
- }
- #endif
-
int board_late_init(void)
{
- u32 reg = 0;
+ u32 ver, reg = 0;
u8 bootmode;
const char *mode;
char *new_targets;
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
+CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
+ CONFIG_MMC_SDHCI=y
CONFIG_NAND_ARASAN=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="MINI_EMMC"
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
++CONFIG_MMC_SDHCI=y
+# CONFIG_EFI_LOADER is not set
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
++CONFIG_AHCI=y
+ CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
+CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
+ CONFIG_MMC_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
--- /dev/null
- CONFIG_HUSH_PARSER=y
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm017_dc3"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ZYNQMP_USB=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm017 dc3"
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm017-dc3"
++CONFIG_AHCI=y
++CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
++# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_OS_BOOT=y
- CONFIG_CMD_DHCP=y
- CONFIG_CMD_MII=y
- CONFIG_CMD_PING=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
- CONFIG_CMD_EXT2=y
- CONFIG_CMD_EXT4=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
- CONFIG_CMD_FAT=y
- CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
++CONFIG_DM_SCSI=y
++CONFIG_SATA_CEVA=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
++CONFIG_MMC_SDHCI=y
+CONFIG_NAND_ARASAN=y
+CONFIG_DM_ETH=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
- CONFIG_HUSH_PARSER=y
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ZYNQMP_USB=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevB"
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100"
++CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
++# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_OS_BOOT=y
- CONFIG_CMD_DHCP=y
- CONFIG_CMD_MII=y
- CONFIG_CMD_PING=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
- CONFIG_CMD_EXT2=y
- CONFIG_CMD_EXT4=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
- CONFIG_CMD_FAT=y
- CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
++CONFIG_MMC_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
- CONFIG_HUSH_PARSER=y
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BOOT_INIT_FILE="board/xilinx/zynqmp/zynqmp-zcu100-revA/regs.txt"
+CONFIG_ZYNQMP_QSPI=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevA"
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revA"
++CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
++# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_OS_BOOT=y
- CONFIG_CMD_DHCP=y
- CONFIG_CMD_MII=y
- CONFIG_CMD_PING=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
- CONFIG_CMD_EXT2=y
- CONFIG_CMD_EXT4=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
- CONFIG_CMD_FAT=y
- CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
++CONFIG_MMC_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
+CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
+ CONFIG_MMC_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
+CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
+ CONFIG_MMC_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
--- /dev/null
- CONFIG_HUSH_PARSER=y
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu106"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ZYNQMP_QSPI=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU106"
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu106"
++CONFIG_AHCI=y
++CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
++# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_OS_BOOT=y
- CONFIG_CMD_DHCP=y
- CONFIG_CMD_MII=y
- CONFIG_CMD_PING=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
- CONFIG_CMD_EXT2=y
- CONFIG_CMD_EXT4=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
- CONFIG_CMD_FAT=y
- CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
++CONFIG_DM_SCSI=y
++CONFIG_SATA_CEVA=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
++CONFIG_MMC_SDHCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQ_SDHCI=y
++CONFIG_MMC_SDHCI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_NO_FLASH=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_ZYNQ_AES=y
+CONFIG_CMD_ZYNQ_RSA=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_ZYNQ_SDHCI=y
++CONFIG_MMC_SDHCI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
+ CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_ZYNQ_SDHCI=y
+ CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_SDHCI=y
+ CONFIG_MMC_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+ CONFIG_CMD_NAND=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
#define CMD_WRITE_DISABLE 0x04
#define CMD_WRITE_ENABLE 0x06
#define CMD_QUAD_PAGE_PROGRAM 0x32
- #define CMD_WRITE_EVCR 0x61
-
- #define CMD_READ_CONFIG 0x35
- #define CMD_FLAG_STATUS 0x70
+/* Used for Micron, Macronix and Winbond flashes */
+#define CMD_ENTER_4B_ADDR 0xB7
+#define CMD_EXIT_4B_ADDR 0xE9
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
DECLARE_GLOBAL_DATA_PTR;
-static void spi_flash_addr(u32 addr, u8 *cmd)
+static void spi_flash_addr(u32 addr, u8 *cmd, u8 four_byte)
{
/* cmd[0] is actual command */
- cmd[1] = addr >> 16;
- cmd[2] = addr >> 8;
- cmd[3] = addr >> 0;
+ if (four_byte) {
+ cmd[1] = addr >> 24;
+ cmd[2] = addr >> 16;
+ cmd[3] = addr >> 8;
+ cmd[4] = addr >> 0;
+ } else {
+ cmd[1] = addr >> 16;
+ cmd[2] = addr >> 8;
+ cmd[3] = addr >> 0;
+ }
}
- /* Read commands array */
- static u8 spi_read_cmds_array[] = {
- CMD_READ_ARRAY_SLOW,
- CMD_READ_ARRAY_FAST,
- CMD_READ_DUAL_OUTPUT_FAST,
- CMD_READ_DUAL_IO_FAST,
- CMD_READ_QUAD_OUTPUT_FAST,
- CMD_READ_QUAD_IO_FAST,
- };
-
static int read_sr(struct spi_flash *flash, u8 *rs)
{
int ret;
#endif
#ifdef CONFIG_SPI_FLASH_BAR
- static int spi_flash_write_bar(struct spi_flash *flash, u32 offset)
+ static int write_bar(struct spi_flash *flash, u32 offset)
{
- u8 cmd, bank_sel;
+ u8 cmd, bank_sel, upage_curr;
int ret;
bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
return flash->bank_curr;
}
- static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0)
+ static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
{
u8 curr_bank = 0;
+#ifdef CONFIG_SPI_GENERIC
+ u8 curr_bank_up = 0;
+#endif
int ret;
if (flash->size <= SPI_FLASH_16MB_BOUN)
flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
}
- ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
- &curr_bank, 1);
- if (ret) {
- debug("SF: fail to read bank addr register\n");
- return ret;
+#ifdef CONFIG_SPI_GENERIC
+ if (flash->dual_flash == SF_DUAL_PARALLEL_FLASH) {
+ flash->spi->flags |= SPI_XFER_LOWER;
+ ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
+ &curr_bank, 1);
+ if (ret)
+ return ret;
+
+ flash->spi->flags |= SPI_XFER_UPPER;
+ ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
+ &curr_bank_up, 1);
+ if (ret)
+ return ret;
+ if (curr_bank != curr_bank_up) {
+ printf("Incorrect Bank selections Dual parallel\n");
+ return -EINVAL;
+ }
+ } else {
+#endif
+ ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
+ &curr_bank, 1);
+ if (ret) {
+ debug("SF: fail to read bank addr register\n");
+ return ret;
+ }
+#ifdef CONFIG_SPI_GENERIC
}
+#endif
- bank_end:
+ bar_end:
flash->bank_curr = curr_bank;
return 0;
}
#ifdef CONFIG_SF_DUAL_FLASH
if (flash->dual_flash > SF_SINGLE_FLASH)
spi_flash_dual(flash, &erase_addr);
+ if (flash->dual_flash == SF_DUAL_STACKED_FLASH)
+ bank_addr = erase_addr;
#endif
+
+ if (flash->spi->bytemode != SPI_4BYTE_MODE) {
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_write_bar(flash, bank_addr);
- ret = write_bar(flash, erase_addr);
- if (ret < 0)
- return ret;
++ ret = write_bar(flash, bank_addr);
+ if (ret < 0)
+ return ret;
#endif
- spi_flash_addr(erase_addr, cmd);
+ spi_flash_addr(erase_addr, cmd, 0);
+ cmdlen = SPI_FLASH_CMD_LEN;
+ } else {
+ spi_flash_addr(erase_addr, cmd, 1);
+ cmdlen = SPI_FLASH_CMD_LEN + 1;
+ }
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
cmd[2], cmd[3], erase_addr);
#ifdef CONFIG_SF_DUAL_FLASH
if (flash->dual_flash > SF_SINGLE_FLASH)
spi_flash_dual(flash, &write_addr);
+ if (flash->dual_flash == SF_DUAL_STACKED_FLASH)
+ bank_addr = write_addr;
#endif
+
+ if (flash->spi->bytemode != SPI_4BYTE_MODE) {
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_write_bar(flash, bank_addr);
- ret = write_bar(flash, write_addr);
- if (ret < 0)
- return ret;
++ ret = write_bar(flash, bank_addr);
+ if (ret < 0)
+ return ret;
#endif
+ }
+
byte_addr = offset % page_size;
chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
+ struct spi_slave *spi = flash->spi;
u8 *cmd, cmdsz;
- u32 remain_len, read_len, read_addr;
+ u32 remain_len, read_len, read_addr, bank_addr;
int bank_sel = 0;
int ret = -1;
#ifdef CONFIG_SF_DUAL_FLASH
if (flash->dual_flash > SF_SINGLE_FLASH)
spi_flash_dual(flash, &read_addr);
+ if (flash->dual_flash == SF_DUAL_STACKED_FLASH)
+ bank_addr = read_addr;
#endif
+
+ if (flash->spi->bytemode != SPI_4BYTE_MODE) {
#ifdef CONFIG_SPI_FLASH_BAR
- bank_sel = spi_flash_write_bar(flash, bank_addr);
- ret = write_bar(flash, read_addr);
- if (ret < 0)
- return ret;
- bank_sel = flash->bank_curr;
++ bank_sel = write_bar(flash, bank_addr);
+ if (bank_sel < 0)
+ return ret;
+ if ((flash->dual_flash == SF_DUAL_STACKED_FLASH) &&
+ (flash->spi->flags & SPI_XFER_U_PAGE))
+ bank_sel += (flash->size >> 1)/
+ SPI_FLASH_16MB_BOUN;
#endif
- remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
- (bank_sel + 1)) - offset;
- if (len < remain_len)
- read_len = len;
- else
- read_len = remain_len;
+ remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
+ (bank_sel + 1)) - offset;
+ if (len < remain_len)
+ read_len = len;
+ else
+ read_len = remain_len;
+ } else {
+ if (len > (SPI_FLASH_16MB_BOUN << flash->shift))
+ read_len = SPI_FLASH_16MB_BOUN << flash->shift;
+ else
+ read_len = len;
+ }
- spi_flash_addr(read_addr, cmd);
+ if (flash->spi->bytemode == SPI_4BYTE_MODE)
+ spi_flash_addr(read_addr, cmd, 1);
+ else
+ spi_flash_addr(read_addr, cmd, 0);
+ debug("%s: Byte Mode:0x%x\n", __func__, flash->spi->bytemode);
+#ifdef CONFIG_SPI_GENERIC
+ if (flash->dual_flash == SF_DUAL_PARALLEL_FLASH)
+ flash->spi->flags |= SPI_XFER_STRIPE;
+#endif
ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
if (ret < 0) {
debug("SF: read failed\n");
#endif
-#ifdef CONFIG_SPI_FLASH_MACRONIX
+#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
- static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+ static int macronix_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
+#ifdef CONFIG_SPI_GENERIC
+ u8 qeb_status_up;
+#endif
int ret;
+#ifdef CONFIG_SPI_GENERIC
+ if (flash->dual_flash & SF_DUAL_PARALLEL_FLASH)
+ flash->spi->flags |= SPI_XFER_LOWER;
+#endif
+
ret = read_sr(flash, &qeb_status);
if (ret < 0)
return ret;
#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
- static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+ static int spansion_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
+#ifdef CONFIG_SPI_GENERIC
+ u8 qeb_status_up;
+#endif
int ret;
+#ifdef CONFIG_SPI_GENERIC
+ if (flash->dual_flash & SF_DUAL_PARALLEL_FLASH)
+ flash->spi->flags |= SPI_XFER_LOWER;
+#endif
+
ret = read_cr(flash, &qeb_status);
if (ret < 0)
return ret;
}
#endif
- static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
++
+ static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
{
- switch (idcode0) {
- #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
+ int tmp;
+ u8 id[SPI_FLASH_MAX_ID_LEN];
+ const struct spi_flash_info *info;
+
++#ifdef CONFIG_SPI_GENERIC
++ if (flash->spi->option & SF_DUAL_PARALLEL_FLASH)
++ flash->spi->flags |= SPI_XFER_LOWER;
++#endif
++
+ tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN);
+ if (tmp < 0) {
+ printf("SF: error %d reading JEDEC ID\n", tmp);
+ return ERR_PTR(tmp);
+ }
+
+ info = spi_flash_ids;
+ for (; info->name != NULL; info++) {
+ if (info->id_len) {
+ if (!memcmp(info->id, id, info->id_len))
+ return info;
+ }
+ }
+
+ printf("SF: unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
+ id[0], id[1], id[2]);
+ return ERR_PTR(-ENODEV);
+ }
+
+ static int set_quad_mode(struct spi_flash *flash,
+ const struct spi_flash_info *info)
+ {
+ switch (JEDEC_MFR(info)) {
+ #ifdef CONFIG_SPI_FLASH_MACRONIX
case SPI_FLASH_CFI_MFR_MACRONIX:
- case SPI_FLASH_CFI_MFR_ISSI:
- return spi_flash_set_qeb_mxic(flash);
+ return macronix_quad_enable(flash);
#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
case SPI_FLASH_CFI_MFR_SPANSION:
int spi_flash_scan(struct spi_flash *flash)
{
struct spi_slave *spi = flash->spi;
- const struct spi_flash_params *params;
- u16 jedec, ext_jedec;
- u8 idcode[6];
- #ifdef CONFIG_SPI_GENERIC
- u8 idcode_up[6];
- u8 i;
- #endif
- u8 cmd;
+ const struct spi_flash_info *info = NULL;
int ret;
- #ifdef CONFIG_SPI_GENERIC
- if (spi->option & SF_DUAL_PARALLEL_FLASH)
- flash->spi->flags |= SPI_XFER_LOWER;
- #endif
-
- /* Read the ID codes */
- ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
- if (ret) {
- printf("SF: Failed to get idcodes\n");
- return -EINVAL;
- }
-
- #ifdef CONFIG_SPI_GENERIC
- if (spi->option == SF_DUAL_PARALLEL_FLASH) {
- spi->flags |= SPI_XFER_UPPER;
- ret = spi_flash_cmd(spi, CMD_READ_ID, idcode_up,
- sizeof(idcode_up));
- if (ret) {
- printf("SF: Failed to get idcodes\n");
- return -EINVAL;
- }
- for (i = 0; i < sizeof(idcode); i++) {
- if (idcode[i] != idcode_up[i]) {
- printf("SF: Failed to get same idcodes\n");
- return -EINVAL;
- }
- }
- }
- #endif
-
- #ifdef DEBUG
- printf("SF: Got idcodes\n");
- print_buffer(0, idcode, 1, sizeof(idcode), 0);
- #endif
-
- jedec = idcode[1] << 8 | idcode[2];
- ext_jedec = idcode[3] << 8 | idcode[4];
-
- /* Validate params from spi_flash_params table */
- params = spi_flash_params_table;
- for (; params->name != NULL; params++) {
- if ((params->jedec >> 16) == idcode[0]) {
- if ((params->jedec & 0xFFFF) == jedec) {
- if (params->ext_jedec == 0)
- break;
- else if (params->ext_jedec == ext_jedec)
- break;
- }
- }
- }
-
- if (!params->name) {
- printf("SF: Unsupported flash IDs: ");
- printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
- idcode[0], jedec, ext_jedec);
- return -EPROTONOSUPPORT;
- }
-
- #ifdef CONFIG_SPI_FLASH_SPANSION
- /*
- * The S25FS-S family physical sectors may be configured as a
- * hybrid combination of eight 4-kB parameter sectors
- * at the top or bottom of the address space with all
- * but one of the remaining sectors being uniform size.
- * The Parameter Sector Erase commands (20h or 21h) must
- * be used to erase the 4-kB parameter sectors individually.
- * The Sector (uniform sector) Erase commands (D8h or DCh)
- * must be used to erase any of the remaining
- * sectors, including the portion of highest or lowest address
- * sector that is not overlaid by the parameter sectors.
- * The uniform sector erase command has no effect on parameter sectors.
- */
- if ((jedec == 0x0219 || (jedec == 0x0220)) &&
- (ext_jedec & 0xff00) == 0x4d00) {
- int ret;
- u8 id[6];
-
- /* Read the ID codes again, 6 bytes */
- ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
- if (ret)
- return -EIO;
-
- ret = memcmp(id, idcode, 5);
- if (ret)
- return -EIO;
+ info = spi_flash_read_id(flash);
+ if (IS_ERR_OR_NULL(info))
+ return -ENOENT;
- /* 0x81: S25FS-S family 0x80: S25FL-S family */
- if (id[5] == 0x81) {
- ret = spansion_s25fss_disable_4KB_erase(spi);
- if (ret)
- return ret;
- }
- }
- #endif
/* Flash powers up read-only, so clear BP# bits */
- if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL ||
- idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX ||
- idcode[0] == SPI_FLASH_CFI_MFR_SST)
+ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
+ JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX ||
+ JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST)
write_sr(flash, 0);
- /* Assign spi data */
- flash->name = params->name;
+ flash->name = info->name;
flash->memory_map = spi->memory_map;
+ flash->dual_flash = flash->spi->option;
- /* Assign spi flash flags */
- if (params->flags & SST_WR)
+ if (info->flags & SST_WR)
flash->flags |= SNOR_F_SST_WR;
- /* Assign spi_flash ops */
#ifndef CONFIG_DM_SPI_FLASH
flash->write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
* the 0x4d00 Extended JEDEC code have 512b pages. All of the others
* have 256b pages.
*/
- if (ext_jedec == 0x4d00) {
- if ((jedec == 0x0215) || (jedec == 0x216) || (jedec == 0x220))
- flash->page_size = 256;
- else
+ if (JEDEC_EXT(info) == 0x4d00) {
+ if ((JEDEC_ID(info) != 0x0215) &&
+ (JEDEC_ID(info) != 0x0216))
flash->page_size = 512;
- } else {
- flash->page_size = 256;
}
flash->page_size <<= flash->shift;
- flash->sector_size = params->sector_size << flash->shift;
- flash->size = flash->sector_size * params->nr_sectors;
+ flash->sector_size = info->sector_size << flash->shift;
- flash->size = flash->sector_size * info->n_sectors << flash->shift;
++ flash->size = flash->sector_size * info->n_sectors;
+
+ /*
+ * So far, the 4-byte address mode haven't been supported in U-Boot,
+ * and make sure the chip (> 16MiB) in default 3-byte address mode,
+ * in case of warm bootup, the chip was set to 4-byte mode in kernel.
+ */
+ if ((flash->size >> flash->shift) > SPI_FLASH_16MB_BOUN) {
+ if (flash->spi->bytemode == SPI_4BYTE_MODE) {
+ if (spi_flash_cmd_4B_addr_switch(flash, true,
- idcode[0]) < 0)
++ JEDEC_MFR(info)) < 0)
+ printf("SF: enter 4B address mode failed\n");
+ } else {
+ if (spi_flash_cmd_4B_addr_switch(flash, false,
- idcode[0]) < 0)
++ JEDEC_MFR(info)) < 0)
+ printf("SF: enter 3B address mode failed\n");
+ }
+ } else {
+ /*
+ * Clear the 4-byte support if the flash size is
+ * less than 16MB
+ */
+ if (flash->spi->bytemode == SPI_4BYTE_MODE)
+ flash->spi->bytemode = 0;
+ }
+
#ifdef CONFIG_SF_DUAL_FLASH
if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
flash->size <<= 1;
/* Now erase size becomes valid sector size */
flash->sector_size = flash->erase_size;
- /* Look for the fastest read cmd */
- cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
- if (cmd) {
- if (flash->spi->dio != SF_DUALIO_FLASH) {
- if ((idcode[0] == SPI_FLASH_CFI_MFR_SPANSION) &&
- (idcode[5] == SPI_FLASH_SPANSION_S25FS_FMLY)) {
- flash->read_cmd = CMD_READ_QUAD_IO_FAST;
- } else {
- cmd = spi_read_cmds_array[cmd - 1];
- flash->read_cmd = cmd;
- }
- } else {
- flash->read_cmd = CMD_READ_DUAL_IO_FAST;
- }
- } else {
- if (idcode[0] == SPI_FLASH_CFI_MFR_ISSI)
- /* Look for read commands */
+ flash->read_cmd = CMD_READ_ARRAY_FAST;
- if (spi->mode & SPI_RX_SLOW)
++ if (spi->mode & SPI_RX_SLOW) {
+ flash->read_cmd = CMD_READ_ARRAY_SLOW;
- else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD)
++ } else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD) {
+ flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST;
- else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL)
++ if (((JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SPANSION) &&
++ (info->id[5] == SPI_FLASH_SPANSION_S25FS_FMLY)) ||
++ (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ISSI))
+ flash->read_cmd = CMD_READ_QUAD_IO_FAST;
- else
- /* Go for default supported read cmd */
- flash->read_cmd = CMD_READ_ARRAY_FAST;
++ } else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL) {
+ flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST;
+ }
+
- /* Not require to look for fastest only two write cmds yet */
- if ((params->flags & WR_QPP) &&
- (flash->spi->op_mode_tx & SPI_OPM_TX_QPP) &&
- (flash->spi->dio != SF_DUALIO_FLASH)) {
- if ((idcode[0] == SPI_FLASH_CFI_MFR_SPANSION) &&
- (idcode[5] == SPI_FLASH_SPANSION_S25FS_FMLY))
++ if (spi->dio == SF_DUALIO_FLASH)
++ flash->read_cmd = CMD_READ_DUAL_IO_FAST;
+
- /* Look for write commands */
- if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
- flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
- else
++ if ((info->flags & WR_QPP) && (spi->mode & SPI_TX_QUAD) &&
++ (spi->dio != SF_DUALIO_FLASH)) {
++ if ((JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SPANSION) &&
++ (info->id[5] == SPI_FLASH_SPANSION_S25FS_FMLY))
+ flash->write_cmd = CMD_PAGE_PROGRAM;
+ else
+ flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
+ } else {
/* Go for default supported write cmd */
flash->write_cmd = CMD_PAGE_PROGRAM;
+ }
+
+
/* Set the quad enable bit - only for quad commands */
if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
(flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
(flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
- if (spi_flash_set_qeb(flash, idcode[0])) {
- debug("SF: Fail to set QEB for %02x\n", idcode[0]);
- return 0;
+ ret = set_quad_mode(flash, info);
+ if (ret) {
+ debug("SF: Fail to set QEB for %02x\n",
+ JEDEC_MFR(info));
+ return -EINVAL;
}
- if (spi_flash_set_qeb(flash, idcode[0])) {
+#ifdef CONFIG_SF_DUAL_FLASH
+ if (flash->dual_flash & SF_DUAL_STACKED_FLASH) {
+ flash->spi->flags |= SPI_XFER_U_PAGE;
- idcode[0]);
- return 0;
++ if (set_quad_mode(flash, info)) {
+ debug("SF: Fail to set QEB Upper Flash %02x\n",
++ JEDEC_MFR(info));
++ return -EINVAL;
+ }
+ flash->spi->flags &= ~SPI_XFER_U_PAGE;
+ }
+#endif
}
/* Read dummy_byte: dummy byte is determined based on the
*/
switch (flash->read_cmd) {
case CMD_READ_QUAD_IO_FAST:
- if (idcode[0] == SPI_FLASH_CFI_MFR_ISSI)
++ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ISSI)
+ flash->dummy_byte = 3;
- else if ((idcode[0] == SPI_FLASH_CFI_MFR_SPANSION) &&
- (idcode[5] == SPI_FLASH_SPANSION_S25FS_FMLY))
++ else if ((JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SPANSION) &&
++ (info->id[5] == SPI_FLASH_SPANSION_S25FS_FMLY))
+ if (flash->dual_flash & SF_DUAL_PARALLEL_FLASH)
+ flash->dummy_byte = 7;
+ else
+ flash->dummy_byte = 5;
+ else
flash->dummy_byte = 2;
break;
case CMD_READ_ARRAY_SLOW:
struct xilinx_spi_regs *regs;
unsigned int freq;
unsigned int mode;
+ unsigned int fifo_depth;
};
-static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
+static int xilinx_spi_child_pre_probe(struct udevice *bus)
+{
+ struct spi_slave *slave = dev_get_parent_priv(bus);
+ struct udevice *dev = dev_get_parent(bus);
+ int spimode;
+
+ spimode = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "xlnx,spi-mode",
+ -1);
+
+ if (spimode == XILINX_SPI_QUAD_MODE)
- slave->op_mode_rx = SPI_OPM_RX_QOF;
++ slave->mode = SPI_RX_QUAD;
+
+ return 0;
+}
+
static int xilinx_spi_probe(struct udevice *bus)
{
struct xilinx_spi_priv *priv = dev_get_priv(bus);
writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr);
/* Clear the RX FIFO */
- while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
+ while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMTY_MASK)
readl(®s->drxr);
- /* Clear Interrupts */
- writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->isr);
+ debug("%s is_dual:0x%x, is_dio:0x%x\n", __func__, priv->is_dual, priv->is_dio);
+
+ writel(0x7F, ®s->isr);
+ config_reg = readl(®s->confr);
+ config_reg &= ~ZYNQ_QSPI_CONFIG_MSA_MASK;
+ config_reg |= ZYNQ_QSPI_CONFIG_IFMODE_MASK |
+ ZYNQ_QSPI_CONFIG_MCS_MASK | ZYNQ_QSPI_CONFIG_PCS_MASK |
+ ZYNQ_QSPI_CONFIG_FW_MASK | ZYNQ_QSPI_CONFIG_MSTREN_MASK;
+ if (priv->is_dual == SF_DUAL_STACKED_FLASH)
+ config_reg |= 0x10;
+ writel(config_reg, ®s->confr);
+
+ if (priv->is_dual == SF_DUAL_PARALLEL_FLASH) {
+ if (priv->is_dio == SF_DUALIO_FLASH)
+ /* Enable two memories on seperate buses */
+ writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK |
+ ZYNQ_QSPI_LCFG_SEP_BUS_MASK |
+ (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) |
+ ZYNQ_QSPI_FR_DUALIO_CODE),
+ ®s->lcr);
+ else
+ /* Enable two memories on seperate buses */
+ writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK |
+ ZYNQ_QSPI_LCFG_SEP_BUS_MASK |
+ (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) |
+ ZYNQ_QSPI_FR_QOUT_CODE),
+ ®s->lcr);
+ } else if (priv->is_dual == SF_DUAL_STACKED_FLASH) {
+ if (priv->is_dio == SF_DUALIO_FLASH)
+ /* Configure two memories on shared bus
+ * by enabling lower mem */
+ writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK |
+ (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) |
+ ZYNQ_QSPI_FR_DUALIO_CODE),
+ ®s->lcr);
+ else
+ /* Configure two memories on shared bus
+ * by enabling lower mem */
+ writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK |
+ (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) |
+ ZYNQ_QSPI_FR_QOUT_CODE),
+ ®s->lcr);
+ }
+ writel(ZYNQ_QSPI_ENABLE_ENABLE_MASK, ®s->enbr);
+}
- /* Manual slave select and Auto start */
- confr = readl(®s->cr);
- confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
- confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
- ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
- ZYNQ_QSPI_CR_MSTREN_MASK;
- writel(confr, ®s->cr);
+/*
+ * zynq_qspi_check_is_dual_flash - checking for dual or single qspi
+ *
+ * This function will check the type of the flash whether it supports
+ * single or dual qspi based on the MIO configuration done by FSBL.
+ *
+ * User needs to correctly configure the MIO's based on the
+ * number of qspi flashes present on the board.
+ *
+ * function will return -1, if there is no MIO configuration for
+ * qspi flash.
+ */
+static void zynq_qspi_check_is_dual_flash(struct zynq_qspi_priv *priv)
+{
+ int lower_mio = 0, upper_mio = 0, upper_mio_cs1 = 0;
- /* Disable the LQSPI feature */
- confr = readl(®s->lqspicfg);
- confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
- writel(confr, ®s->lqspicfg);
+ priv->is_dual = -1;
+ priv->is_dio = 0;
+ lower_mio = zynq_slcr_get_mio_pin_status("qspi0");
+ if (lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0) {
+ priv->is_dual = SF_SINGLE_FLASH;
+ } else {
+ lower_mio = zynq_slcr_get_mio_pin_status("qspi0_dio");
+ if (lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0_DIO) {
+ debug("QSPI in Single 2-bit\n");
+ priv->is_dio = SF_DUALIO_FLASH;
+ priv->is_dual = SF_SINGLE_FLASH;
+ }
+ }
- /* Enable SPI */
- writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
+ if (priv->is_dio != SF_DUALIO_FLASH) {
+ upper_mio_cs1 = zynq_slcr_get_mio_pin_status("qspi1_cs");
+ if ((lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0) &&
+ (upper_mio_cs1 == ZYNQ_QSPI_MIO_NUM_QSPI1_CS))
+ priv->is_dual = SF_DUAL_STACKED_FLASH;
+
+ upper_mio = zynq_slcr_get_mio_pin_status("qspi1");
+ if ((lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0) &&
+ (upper_mio_cs1 == ZYNQ_QSPI_MIO_NUM_QSPI1_CS) &&
+ (upper_mio == ZYNQ_QSPI_MIO_NUM_QSPI1))
+ priv->is_dual = SF_DUAL_PARALLEL_FLASH;
+ } else {
+ upper_mio_cs1 = zynq_slcr_get_mio_pin_status("qspi1_cs_dio");
+ if ((lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0_DIO) &&
+ (upper_mio_cs1 == ZYNQ_QSPI_MIO_NUM_QSPI1_CS_DIO)) {
+ debug("QSPI in DualStacked 2-bit\n");
+ priv->is_dual = SF_DUAL_STACKED_FLASH;
+ }
+ upper_mio = zynq_slcr_get_mio_pin_status("qspi1_dio");
+ if ((lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0_DIO) &&
+ (upper_mio_cs1 == ZYNQ_QSPI_MIO_NUM_QSPI1_CS_DIO) &&
+ (upper_mio == ZYNQ_QSPI_MIO_NUM_QSPI1_DIO)) {
+ debug("QSPI in DualParallel 2-bit\n");
+ priv->is_dual = SF_DUAL_PARALLEL_FLASH;
+ }
+ }
+}
+
+static int zynq_qspi_child_pre_probe(struct udevice *bus)
+{
+ struct spi_slave *slave = dev_get_parent_priv(bus);
+ struct zynq_qspi_priv *priv = dev_get_priv(bus->parent);
+
+ slave->option = priv->is_dual;
+ slave->dio = priv->is_dio;
- slave->op_mode_rx = SPI_OPM_RX_QOF;
- slave->op_mode_tx = SPI_OPM_TX_QPP;
++ slave->mode = SPI_RX_QUAD | SPI_TX_QUAD;
+
+ return 0;
}
static int zynq_qspi_probe(struct udevice *bus)
--- /dev/null
- slave->op_mode_rx = SPI_OPM_RX_QOF;
- slave->op_mode_tx = SPI_OPM_TX_QPP;
+/*
+ * (C) Copyright 2014 - 2015 Xilinx
+ *
+ * Xilinx ZynqMP Quad-SPI(QSPI) controller driver (master mode only)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <ubi_uboot.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clk.h>
+#include "../mtd/spi/sf_internal.h"
+
+#define ZYNQMP_QSPI_GFIFO_STRT_MODE_MASK (1 << 29)
+#define ZYNQMP_QSPI_CONFIG_MODE_EN_MASK (3 << 30)
+#define ZYNQMP_QSPI_CONFIG_DMA_MODE (2 << 30)
+#define ZYNQMP_QSPI_CONFIG_CPHA_MASK (1 << 2)
+#define ZYNQMP_QSPI_CONFIG_CPOL_MASK (1 << 1)
+
+/* QSPI MIO's count for different connection topologies */
+#define ZYNQMP_QSPI_MIO_NUM_QSPI0 6
+#define ZYNQMP_QSPI_MIO_NUM_QSPI1 5
+#define ZYNQMP_QSPI_MIO_NUM_QSPI1_CS 1
+
+/*
+ * QSPI Interrupt Registers bit Masks
+ *
+ * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
+ * bit definitions.
+ */
+#define ZYNQMP_QSPI_IXR_TXNFULL_MASK 0x00000004 /* QSPI TX FIFO Overflow */
+#define ZYNQMP_QSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */
+#define ZYNQMP_QSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */
+#define ZYNQMP_QSPI_IXR_GFEMTY_MASK 0x00000080 /* QSPI Generic FIFO Empty */
+#define ZYNQMP_QSPI_IXR_ALL_MASK (ZYNQMP_QSPI_IXR_TXNFULL_MASK | \
+ ZYNQMP_QSPI_IXR_RXNEMTY_MASK)
+
+/*
+ * QSPI Enable Register bit Masks
+ *
+ * This register is used to enable or disable the QSPI controller
+ */
+#define ZYNQMP_QSPI_ENABLE_ENABLE_MASK 0x00000001 /* QSPI Enable Bit Mask */
+
+#define ZYNQMP_QSPI_GFIFO_LOW_BUS (1 << 14)
+#define ZYNQMP_QSPI_GFIFO_CS_LOWER (1 << 12)
+#define ZYNQMP_QSPI_GFIFO_UP_BUS (1 << 15)
+#define ZYNQMP_QSPI_GFIFO_CS_UPPER (1 << 13)
+#define ZYNQMP_QSPI_SPI_MODE_QSPI (3 << 10)
+#define ZYNQMP_QSPI_SPI_MODE_SPI (1 << 10)
+#define ZYNQMP_QSPI_IMD_DATA_CS_ASSERT 5
+#define ZYNQMP_QSPI_IMD_DATA_CS_DEASSERT 5
+#define ZYNQMP_QSPI_GFIFO_TX (1 << 16)
+#define ZYNQMP_QSPI_GFIFO_RX (1 << 17)
+#define ZYNQMP_QSPI_GFIFO_STRIPE_MASK (1 << 18)
+#define ZYNQMP_QSPI_GFIFO_IMD_MASK 0xFF
+#define ZYNQMP_QSPI_GFIFO_EXP_MASK (1 << 9)
+#define ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK (1 << 8)
+#define ZYNQMP_QSPI_STRT_GEN_FIFO (1 << 28)
+#define ZYNQMP_QSPI_GEN_FIFO_STRT_MOD (1 << 29)
+#define ZYNQMP_QSPI_GFIFO_WP_HOLD (1 << 19)
+#define ZYNQMP_QSPI_BAUD_DIV_MASK (7 << 3)
+#define ZYNQMP_QSPI_DFLT_BAUD_RATE_DIV (1 << 3)
+#define ZYNQMP_QSPI_GFIFO_ALL_INT_MASK 0xFBE
+#define ZYNQMP_QSPI_DMA_DST_I_STS_DONE (1 << 1)
+#define ZYNQMP_QSPI_DMA_DST_I_STS_MASK 0xFE
+#define MODEBITS 0x6
+
+#define QUAD_OUT_READ_CMD 0x6B
+#define QUAD_PAGE_PROGRAM_CMD 0x32
+
+#define ZYNQMP_QSPI_GFIFO_SELECT (1 << 0)
+
+#define ZYNQMP_QSPI_FIFO_THRESHOLD 1
+
+#define SPI_XFER_ON_BOTH 0
+#define SPI_XFER_ON_LOWER 1
+#define SPI_XFER_ON_UPPER 2
+
+#define ZYNQMP_QSPI_DMA_ALIGN 0x4
+#define ZYNQMP_QSPI_MAX_BAUD_RATE_VAL 7
+
+#define ZYNQMP_QSPI_TIMEOUT 100000000
+
+/* QSPI register offsets */
+struct zynqmp_qspi_regs {
+ u32 confr; /* 0x00 */
+ u32 isr; /* 0x04 */
+ u32 ier; /* 0x08 */
+ u32 idisr; /* 0x0C */
+ u32 imaskr; /* 0x10 */
+ u32 enbr; /* 0x14 */
+ u32 dr; /* 0x18 */
+ u32 txd0r; /* 0x1C */
+ u32 drxr; /* 0x20 */
+ u32 sicr; /* 0x24 */
+ u32 txftr; /* 0x28 */
+ u32 rxftr; /* 0x2C */
+ u32 gpior; /* 0x30 */
+ u32 reserved0; /* 0x34 */
+ u32 lpbkdly; /* 0x38 */
+ u32 reserved1; /* 0x3C */
+ u32 genfifo; /* 0x40 */
+ u32 gqspisel; /* 0x44 */
+ u32 reserved2; /* 0x48 */
+ u32 gqfifoctrl; /* 0x4C */
+ u32 gqfthr; /* 0x50 */
+ u32 gqpollcfg; /* 0x54 */
+ u32 gqpollto; /* 0x58 */
+ u32 gqxfersts; /* 0x5C */
+ u32 gqfifosnap; /* 0x60 */
+ u32 gqrxcpy; /* 0x64 */
+};
+
+struct zynqmp_qspi_dma_regs {
+ u32 dmadst; /* 0x00 */
+ u32 dmasize; /* 0x04 */
+ u32 dmasts; /* 0x08 */
+ u32 dmactrl; /* 0x0C */
+ u32 reserved0; /* 0x10 */
+ u32 dmaisr; /* 0x14 */
+ u32 dmaier; /* 0x18 */
+ u32 dmaidr; /* 0x1C */
+ u32 dmaimr; /* 0x20 */
+ u32 dmactrl2; /* 0x24 */
+ u32 dmadstmsb; /* 0x28 */
+};
+
+struct zynqmp_qspi_platdata {
+ struct zynqmp_qspi_regs *regs;
+ struct zynqmp_qspi_dma_regs *dma_regs;
+ u32 frequency;
+ u32 speed_hz;
+};
+
+struct zynqmp_qspi_priv {
+ struct zynqmp_qspi_regs *regs;
+ struct zynqmp_qspi_dma_regs *dma_regs;
+ u8 mode;
+ u32 freq;
+ const void *tx_buf;
+ void *rx_buf;
+ unsigned len;
+ int bytes_to_transfer;
+ int bytes_to_receive;
+ unsigned int is_inst;
+ unsigned int is_dual;
+ unsigned int u_page;
+ unsigned int bus;
+ unsigned int stripe;
+ unsigned cs_change:1;
+};
+
+static u8 last_cmd;
+
+static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct zynqmp_qspi_platdata *plat = bus->platdata;
+
+ debug("%s\n", __func__);
+
+ plat->regs = (struct zynqmp_qspi_regs *)(dev_get_addr(bus) + 0x100);
+ plat->dma_regs = (struct zynqmp_qspi_dma_regs *)(dev_get_addr(bus) +
+ 0x800);
+
+ plat->frequency = 166666666;
+ plat->speed_hz = plat->frequency / 2;
+
+ return 0;
+}
+
+static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
+{
+ u32 config_reg;
+ struct zynqmp_qspi_regs *regs = priv->regs;
+
+ writel(ZYNQMP_QSPI_GFIFO_SELECT, ®s->gqspisel);
+ writel(ZYNQMP_QSPI_GFIFO_ALL_INT_MASK, ®s->idisr);
+ writel(ZYNQMP_QSPI_FIFO_THRESHOLD, ®s->txftr);
+ writel(ZYNQMP_QSPI_FIFO_THRESHOLD, ®s->rxftr);
+ writel(ZYNQMP_QSPI_GFIFO_ALL_INT_MASK, ®s->isr);
+
+ config_reg = readl(®s->confr);
+ config_reg &= ~(ZYNQMP_QSPI_GFIFO_STRT_MODE_MASK |
+ ZYNQMP_QSPI_CONFIG_MODE_EN_MASK);
+ config_reg |= ZYNQMP_QSPI_CONFIG_DMA_MODE |
+ ZYNQMP_QSPI_GFIFO_WP_HOLD |
+ ZYNQMP_QSPI_DFLT_BAUD_RATE_DIV;
+ writel(config_reg, ®s->confr);
+
+ writel(ZYNQMP_QSPI_ENABLE_ENABLE_MASK, ®s->enbr);
+}
+
+static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
+{
+ u32 gqspi_fifo_reg = 0;
+
+ if (priv->is_dual == SF_DUAL_PARALLEL_FLASH) {
+ if (priv->bus == SPI_XFER_ON_BOTH)
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS |
+ ZYNQMP_QSPI_GFIFO_UP_BUS |
+ ZYNQMP_QSPI_GFIFO_CS_UPPER |
+ ZYNQMP_QSPI_GFIFO_CS_LOWER;
+ else if (priv->bus == SPI_XFER_ON_LOWER)
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS |
+ ZYNQMP_QSPI_GFIFO_CS_UPPER |
+ ZYNQMP_QSPI_GFIFO_CS_LOWER;
+ else if (priv->bus == SPI_XFER_ON_UPPER)
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_UP_BUS |
+ ZYNQMP_QSPI_GFIFO_CS_LOWER |
+ ZYNQMP_QSPI_GFIFO_CS_UPPER;
+ else
+ debug("Wrong Bus selection:0x%x\n", priv->bus);
+ } else {
+ if (priv->u_page)
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS |
+ ZYNQMP_QSPI_GFIFO_CS_UPPER;
+ else
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS |
+ ZYNQMP_QSPI_GFIFO_CS_LOWER;
+ }
+ return gqspi_fifo_reg;
+}
+
+static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
+ u32 gqspi_fifo_reg)
+{
+ struct zynqmp_qspi_regs *regs = priv->regs;
+ u32 reg;
+
+ do {
+ reg = readl(®s->isr);
+ } while (!(reg & ZYNQMP_QSPI_IXR_GFEMTY_MASK));
+
+ writel(gqspi_fifo_reg, ®s->genfifo);
+}
+
+static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
+{
+ u32 gqspi_fifo_reg = 0;
+
+ if (is_on) {
+ gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
+ gqspi_fifo_reg |= ZYNQMP_QSPI_SPI_MODE_SPI |
+ ZYNQMP_QSPI_IMD_DATA_CS_ASSERT;
+ } else {
+ if (priv->is_dual == SF_DUAL_PARALLEL_FLASH)
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_UP_BUS |
+ ZYNQMP_QSPI_GFIFO_LOW_BUS;
+ else if (priv->u_page)
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_UP_BUS;
+ else
+ gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS;
+ gqspi_fifo_reg |= ZYNQMP_QSPI_IMD_DATA_CS_DEASSERT;
+ }
+
+ debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
+
+ zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
+}
+
+static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
+{
+ struct zynqmp_qspi_platdata *plat = bus->platdata;
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+ struct zynqmp_qspi_regs *regs = priv->regs;
+ uint32_t confr;
+ u8 baud_rate_val = 0;
+
+ debug("%s\n", __func__);
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+
+ /* Set the clock frequency */
+ confr = readl(®s->confr);
+ if (speed == 0) {
+ /* Set baudrate x8, if the freq is 0 */
+ baud_rate_val = 0x2;
+ } else if (plat->speed_hz != speed) {
+ while ((baud_rate_val < 8) &&
+ ((plat->frequency /
+ (2 << baud_rate_val)) > speed))
+ baud_rate_val++;
+
+ if (baud_rate_val > ZYNQMP_QSPI_MAX_BAUD_RATE_VAL)
+ baud_rate_val = ZYNQMP_QSPI_MAX_BAUD_RATE_VAL;
+
+ plat->speed_hz = speed / (2 << baud_rate_val);
+ }
+ confr &= ~ZYNQMP_QSPI_BAUD_DIV_MASK;
+ confr |= (baud_rate_val << 3);
+ writel(confr, ®s->confr);
+
+ priv->freq = speed;
+
+ debug("regs=%p, mode=%d\n", priv->regs, priv->freq);
+
+ return 0;
+}
+
+static int zynqmp_qspi_child_pre_probe(struct udevice *bus)
+{
+ struct spi_slave *slave = dev_get_parent_priv(bus);
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus->parent);
+
+ slave->option = priv->is_dual;
++ slave->mode = SPI_RX_QUAD | SPI_TX_QUAD;
+ slave->bytemode = SPI_4BYTE_MODE;
+
+ return 0;
+}
+
+static void zynqmp_qspi_check_is_dual_flash(struct zynqmp_qspi_priv *priv)
+{
+ int lower_mio = 0, upper_mio = 0, upper_mio_cs1 = 0;
+
+ lower_mio = zynq_slcr_get_mio_pin_status("qspi0");
+ if (lower_mio == ZYNQMP_QSPI_MIO_NUM_QSPI0)
+ priv->is_dual = SF_SINGLE_FLASH;
+
+ upper_mio_cs1 = zynq_slcr_get_mio_pin_status("qspi1_cs");
+ if ((lower_mio == ZYNQMP_QSPI_MIO_NUM_QSPI0) &&
+ (upper_mio_cs1 == ZYNQMP_QSPI_MIO_NUM_QSPI1_CS))
+ priv->is_dual = SF_DUAL_STACKED_FLASH;
+
+ upper_mio = zynq_slcr_get_mio_pin_status("qspi1");
+ if ((lower_mio == ZYNQMP_QSPI_MIO_NUM_QSPI0) &&
+ (upper_mio_cs1 == ZYNQMP_QSPI_MIO_NUM_QSPI1_CS) &&
+ (upper_mio == ZYNQMP_QSPI_MIO_NUM_QSPI1))
+ priv->is_dual = SF_DUAL_PARALLEL_FLASH;
+}
+
+static int zynqmp_qspi_probe(struct udevice *bus)
+{
+ struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus);
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+
+ debug("zynqmp_qspi_probe: bus:%p, priv:%p \n", bus, priv);
+
+ priv->regs = plat->regs;
+ priv->dma_regs = plat->dma_regs;
+ zynqmp_qspi_check_is_dual_flash(priv);
+
+ if (priv->is_dual == -1) {
+ debug("%s: No QSPI device detected based on MIO settings\n",
+ __func__);
+ return -1;
+ }
+
+ /* init the zynq spi hw */
+ zynqmp_qspi_init_hw(priv);
+
+ return 0;
+}
+
+static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
+{
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+ struct zynqmp_qspi_regs *regs = priv->regs;
+ uint32_t confr;
+
+ debug("%s\n", __func__);
+ /* Set the SPI Clock phase and polarities */
+ confr = readl(®s->confr);
+ confr &= ~(ZYNQMP_QSPI_CONFIG_CPHA_MASK |
+ ZYNQMP_QSPI_CONFIG_CPOL_MASK);
+
+ if (priv->mode & SPI_CPHA)
+ confr |= ZYNQMP_QSPI_CONFIG_CPHA_MASK;
+ if (priv->mode & SPI_CPOL)
+ confr |= ZYNQMP_QSPI_CONFIG_CPOL_MASK;
+
+ //writel(confr, ®s->confr);
+ priv->mode = mode;
+
+ debug("regs=%p, mode=%d\n", priv->regs, priv->mode);
+
+ return 0;
+}
+
+
+static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
+{
+ u32 data;
+ u32 timeout = ZYNQMP_QSPI_TIMEOUT;
+ struct zynqmp_qspi_regs *regs = priv->regs;
+ u32 *buf = (u32 *)priv->tx_buf;
+ u32 len = size;
+
+ debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr),
+ size);
+
+ while (size && timeout) {
+ if (readl(®s->isr) &
+ ZYNQMP_QSPI_IXR_TXNFULL_MASK) {
+ if (size >= 4) {
+ writel(*buf, ®s->txd0r);
+ buf++;
+ size -= 4;
+ } else {
+ switch (size) {
+ case 1:
+ data = *((u8 *)buf);
+ buf += 1;
+ data |= 0xFFFFFF00;
+ break;
+ case 2:
+ data = *((u16 *)buf);
+ buf += 2;
+ data |= 0xFFFF0000;
+ break;
+ case 3:
+ data = *((u16 *)buf);
+ buf += 2;
+ data |= (*((u8 *)buf) << 16);
+ buf += 1;
+ data |= 0xFF000000;
+ break;
+ }
+ writel(data, ®s->txd0r);
+ size = 0;
+ }
+ } else {
+ udelay(1);
+ timeout--;
+ }
+ }
+ if (!timeout) {
+ printf("zynqmp_qspi_fill_tx_fifo: Timeout\n");
+ return -1;
+ }
+
+ priv->tx_buf += len;
+ return 0;
+}
+
+static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
+{
+ u8 command = 1;
+ u32 gen_fifo_cmd;
+ u32 bytecount = 0;
+
+ while (priv->len) {
+ gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+ gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_TX;
+
+ if (command) {
+ command = 0;
+ last_cmd = *(u8 *)priv->tx_buf;
+ }
+
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_SPI;
+ gen_fifo_cmd |= *(u8 *)priv->tx_buf;
+ bytecount++;
+ priv->len--;
+ priv->tx_buf = (u8 *)priv->tx_buf + 1;
+
+ debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
+
+ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+ }
+}
+
+static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
+ u32 *gen_fifo_cmd)
+{
+ u32 expval = 8;
+ u32 len;
+
+ while (1) {
+ if (priv->len > 255) {
+ if (priv->len & (1 << expval)) {
+ *gen_fifo_cmd &= ~ZYNQMP_QSPI_GFIFO_IMD_MASK;
+ *gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_EXP_MASK;
+ *gen_fifo_cmd |= expval;
+ priv->len -= (1 << expval);
+ return expval;
+ }
+ expval++;
+ } else {
+ *gen_fifo_cmd &= ~(ZYNQMP_QSPI_GFIFO_IMD_MASK |
+ ZYNQMP_QSPI_GFIFO_EXP_MASK);
+ *gen_fifo_cmd |= (u8)priv->len;
+ len = (u8)priv->len;
+ priv->len = 0;
+ return len;
+ }
+ }
+}
+
+static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
+{
+ u32 gen_fifo_cmd;
+ u32 len;
+ int ret = 0;
+
+ gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+ gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_TX |
+ ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK;
+
+ if (priv->stripe)
+ gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_STRIPE_MASK;
+
+ if (last_cmd == QUAD_PAGE_PROGRAM_CMD)
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_QSPI;
+ else
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_SPI;
+
+ while (priv->len) {
+ len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
+ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+
+ debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
+
+ if (gen_fifo_cmd & ZYNQMP_QSPI_GFIFO_EXP_MASK)
+ ret = zynqmp_qspi_fill_tx_fifo(priv,
+ 1 << len);
+ else
+ ret = zynqmp_qspi_fill_tx_fifo(priv,
+ len);
+
+ if (ret)
+ return ret;
+ }
+ return ret;
+}
+
+static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
+ u32 gen_fifo_cmd, u32 *buf)
+{
+ u32 addr;
+ u32 size, len;
+ u32 timeout = ZYNQMP_QSPI_TIMEOUT;
+ u32 actuallen = priv->len;
+ struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
+
+ writel((unsigned long)buf, &dma_regs->dmadst);
+ writel(roundup(priv->len, 4), &dma_regs->dmasize);
+ writel(ZYNQMP_QSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
+ addr = (unsigned long)buf;
+ size = roundup(priv->len, ARCH_DMA_MINALIGN);
+ flush_dcache_range(addr, addr+size);
+
+ while (priv->len) {
+ len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
+ if (!(gen_fifo_cmd & ZYNQMP_QSPI_GFIFO_EXP_MASK) &&
+ (len % 4)) {
+ gen_fifo_cmd &= ~(0xFF);
+ gen_fifo_cmd |= (len/4 + 1) * 4;
+ }
+ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+
+ debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
+ }
+
+ while (timeout) {
+ if (readl(&dma_regs->dmaisr) &
+ ZYNQMP_QSPI_DMA_DST_I_STS_DONE) {
+ writel(ZYNQMP_QSPI_DMA_DST_I_STS_DONE,
+ &dma_regs->dmaisr);
+ break;
+ }
+ udelay(1);
+ timeout--;
+ }
+
+ debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
+ (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
+ actuallen);
+ if (!timeout) {
+ printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
+ return -1;
+ }
+
+ if (buf != priv->rx_buf)
+ memcpy(priv->rx_buf, buf, actuallen);
+
+ return 0;
+}
+
+static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
+{
+ u32 gen_fifo_cmd;
+ u32 *buf;
+ u32 actuallen = priv->len;
+
+ gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+ gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_RX |
+ ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK;
+
+ if (last_cmd == QUAD_OUT_READ_CMD)
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_QSPI;
+ else
+ gen_fifo_cmd |= ZYNQMP_QSPI_SPI_MODE_SPI;
+
+ if (priv->stripe)
+ gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_STRIPE_MASK;
+
+ /*
+ * Check if receive buffer is aligned to 4 byte and length
+ * is multiples of four byte as we are using dma to receive.
+ */
+ if (!((unsigned long)priv->rx_buf & (ZYNQMP_QSPI_DMA_ALIGN - 1)) &&
+ !(actuallen % ZYNQMP_QSPI_DMA_ALIGN)) {
+ buf = (u32 *)priv->rx_buf;
+ return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
+ }
+
+ ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
+ ZYNQMP_QSPI_DMA_ALIGN));
+ buf = (u32 *)tmp;
+ return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
+}
+
+static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv)
+{
+ int ret = 0;
+
+ if (priv->is_inst) {
+ if (priv->tx_buf)
+ zynqmp_qspi_genfifo_cmd(priv);
+ else
+ ret = -1;
+ } else {
+ if (priv->tx_buf)
+ ret = zynqmp_qspi_genfifo_fill_tx(priv);
+ else if (priv->rx_buf)
+ ret = zynqmp_qspi_genfifo_fill_rx(priv);
+ else
+ ret = -1;
+ }
+ return ret;
+}
+
+static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv)
+{
+ static unsigned cs_change = 1;
+ int status = 0;
+
+ debug("%s\n", __func__);
+
+ while (1) {
+ /* Select the chip if required */
+ if (cs_change)
+ zynqmp_qspi_chipselect(priv, 1);
+
+ cs_change = priv->cs_change;
+
+ if (!priv->tx_buf && !priv->rx_buf && priv->len) {
+ status = -1;
+ break;
+ }
+
+ /* Request the transfer */
+ if (priv->len) {
+ status = zynqmp_qspi_start_transfer(priv);
+ priv->is_inst = 0;
+ if (status < 0)
+ break;
+ }
+
+ if (cs_change)
+ /* Deselect the chip */
+ zynqmp_qspi_chipselect(priv, 0);
+ break;
+ }
+
+ return status;
+}
+
+static int zynqmp_qspi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+ struct zynqmp_qspi_regs *regs = priv->regs;
+
+ debug("%s\n", __func__);
+ writel(ZYNQMP_QSPI_ENABLE_ENABLE_MASK, ®s->enbr);
+
+ return 0;
+}
+
+static int zynqmp_qspi_release_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+ struct zynqmp_qspi_regs *regs = priv->regs;
+
+ debug("%s\n", __func__);
+ writel(~ZYNQMP_QSPI_ENABLE_ENABLE_MASK, ®s->enbr);
+
+ return 0;
+}
+
+int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+
+ debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__,
+ (unsigned long)priv, bitlen, (unsigned long)dout);
+ debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags);
+
+ priv->tx_buf = dout;
+ priv->rx_buf = din;
+ priv->len = bitlen / 8;
+
+ /*
+ * Festering sore.
+ * Assume that the beginning of a transfer with bits to
+ * transmit must contain a device command.
+ */
+ if (dout && flags & SPI_XFER_BEGIN)
+ priv->is_inst = 1;
+ else
+ priv->is_inst = 0;
+
+ if (flags & SPI_XFER_END)
+ priv->cs_change = 1;
+ else
+ priv->cs_change = 0;
+
+ if (flags & SPI_XFER_U_PAGE)
+ priv->u_page = 1;
+ else
+ priv->u_page = 0;
+
+ priv->stripe = 0;
+ priv->bus = 0;
+
+ if (priv->is_dual == SF_DUAL_PARALLEL_FLASH) {
+ if (flags & SPI_XFER_MASK)
+ priv->bus = (flags & SPI_XFER_MASK) >> 8;
+ if (flags & SPI_XFER_STRIPE)
+ priv->stripe = 1;
+ }
+
+ zynqmp_qspi_transfer(priv);
+
+ return 0;
+}
+
+static const struct dm_spi_ops zynqmp_qspi_ops = {
+ .claim_bus = zynqmp_qspi_claim_bus,
+ .release_bus = zynqmp_qspi_release_bus,
+ .xfer = zynqmp_qspi_xfer,
+ .set_speed = zynqmp_qspi_set_speed,
+ .set_mode = zynqmp_qspi_set_mode,
+};
+
+static const struct udevice_id zynqmp_qspi_ids[] = {
+ { .compatible = "xlnx,zynqmp-qspi-1.0" },
+ { }
+};
+
+U_BOOT_DRIVER(zynqmp_qspi) = {
+ .name = "zynqmp_qspi",
+ .id = UCLASS_SPI,
+ .of_match = zynqmp_qspi_ids,
+ .ops = &zynqmp_qspi_ops,
+ .ofdata_to_platdata = zynqmp_qspi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct zynqmp_qspi_platdata),
+ .priv_auto_alloc_size = sizeof(struct zynqmp_qspi_priv),
+ .probe = zynqmp_qspi_probe,
+ .child_pre_probe = zynqmp_qspi_child_pre_probe,
+};
"setenv stdin nc\0" \
"serial=setenv stdout serial;"\
"setenv stdin serial\0"
-
+#endif
+
#define CONFIG_CMDLINE_EDITING
/* Enable flat device tree support */
#endif
#define CONFIG_AUTO_COMPLETE
- /* PXE */
- #define CONFIG_CMD_PXE
- #define CONFIG_MENU
-
+#ifdef CONFIG_ZYNQMP_QSPI
+# define CONFIG_SPI_GENERIC
+# define CONFIG_SF_DEFAULT_SPEED 30000000
+# define CONFIG_SF_DUAL_FLASH
+# define CONFIG_CMD_SF_TEST
+#endif
+
#if defined(CONFIG_ZYNQ_SDHCI)
- # define CONFIG_MMC
# define CONFIG_GENERIC_MMC
# define CONFIG_SUPPORT_EMMC_BOOT
- # define CONFIG_SDHCI
# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000
# endif
#define CONFIG_SYS_LOAD_ADDR 0x8000000
#if defined(CONFIG_ZYNQMP_USB)
- #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_XHCI_ZYNQMP
#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9)
#define CONFIG_ZYNQ_EEPROM
- #define CONFIG_SATA_CEVA
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
- ZYNQMP_USB1_XHCI_BASEADDR}
#define COUNTER_FREQUENCY 4000000
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_SDHCI1
--#define CONFIG_AHCI
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
#include <configs/xilinx_zynqmp.h>
--- /dev/null
- #define CONFIG_AHCI
- #define CONFIG_SATA_CEVA
-
+/*
+ * Configuration for Xilinx ZynqMP zc1751 XM017 DC3
+ *
+ * (C) Copyright 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H
+#define __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H
+
+#define CONFIG_ZYNQ_SDHCI1
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_I2C1
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H */
--- /dev/null
- #define CONFIG_SATA_CEVA
-
+/*
+ * Configuration for Xilinx ZynqMP zcu106
+ *
+ * (C) Copyright 2016 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZCU106_H
+#define __CONFIG_ZYNQMP_ZCU106_H
+
+#define CONFIG_ZYNQ_SDHCI1
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_I2C1
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_NUM_I2C_BUSES 18
+#define CONFIG_SYS_I2C_BUSES { \
+ {0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
+ {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
+ {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
+ {1, {I2C_NULL_HOP} }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
+ {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
+ }
+
+#define CONFIG_SYS_I2C_ZYNQ
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ZYNQ_EEPROM_BUS 5
+#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
+#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZCU106_H */
# define CONFIG_DOS_PARTITION
#endif
- # define CONFIG_CMD_NAND
+/* NAND */
+#ifdef CONFIG_NAND_ZYNQ
- # define CONFIG_SYS_NAND_SELF_INIT
+# define CONFIG_CMD_NAND_LOCK_UNLOCK
+# define CONFIG_SYS_MAX_NAND_DEVICE 1
+# define CONFIG_SYS_NAND_ONFI_DETECTION
+# define CONFIG_MTD_DEVICE
+#endif
+
#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
#define CONFIG_SYS_I2C_ZYNQ
#endif
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds"
+/* FPGA support */
+#define CONFIG_SPL_FPGA_SUPPORT
+#define CONFIG_SPL_FPGA_LOAD_ADDR 0x1000000
+/* #define CONFIG_SPL_FPGA_BIT */
+#ifdef CONFIG_SPL_FPGA_BIT
+# define CONFIG_SPL_FPGA_LOAD_ARGS_NAME "download.bit"
+#else
+# define CONFIG_SPL_FPGA_LOAD_ARGS_NAME "fpga.bin"
+#endif
+
/* MMC support */
#ifdef CONFIG_ZYNQ_SDHCI
- #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
- #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
#define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */
#define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */
#define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */
-#define SPI_RX_SLOW BIT(11) /* receive with 1 wire slow */
-#define SPI_RX_DUAL BIT(12) /* receive with 2 wires */
-#define SPI_RX_QUAD BIT(13) /* receive with 4 wires */
+
+#define SPI_3BYTE_MODE 0x0
+#define SPI_4BYTE_MODE 0x1
+
+/* SPI transfer flags */
+#define SPI_XFER_STRIPE (1 << 6)
+#define SPI_XFER_MASK (3 << 8)
+#define SPI_XFER_LOWER (1 << 8)
+#define SPI_XFER_UPPER (2 << 8)
+
+/* SPI TX operation modes */
+#define SPI_OPM_TX_QPP (1 << 0)
+#define SPI_OPM_TX_BP (1 << 1)
+
+/* SPI RX operation modes */
+#define SPI_OPM_RX_AS (1 << 0)
+#define SPI_OPM_RX_AF (1 << 1)
+#define SPI_OPM_RX_DOUT (1 << 2)
+#define SPI_OPM_RX_DIO (1 << 3)
+#define SPI_OPM_RX_QOF (1 << 4)
+#define SPI_OPM_RX_QIOF (1 << 5)
+#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_AF | SPI_OPM_RX_DOUT | \
+ SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
+ SPI_OPM_RX_QIOF)
+
+/* SPI mode_rx flags */
+#define SPI_RX_SLOW BIT(0) /* receive with 1 wire slow */
+#define SPI_RX_FAST BIT(1) /* receive with 1 wire fast */
+#define SPI_RX_DUAL BIT(2) /* receive with 2 wires */
+#define SPI_RX_QUAD BIT(3) /* receive with 4 wires */
- /* SPI bus connection options - see enum spi_dual_flash */
- #define SPI_CONN_DUAL_SHARED (1 << 0)
- #define SPI_CONN_DUAL_SEPARATED (1 << 1)
-
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
libs-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/
libs-y += drivers/
- libs-$(CONFIG_SPL_DFU_SUPPORT) += drivers/dfu/
- libs-$(CONFIG_SPL_DFU_SUPPORT) += drivers/usb/gadget/
- libs-$(CONFIG_SPL_DFU_SUPPORT) += drivers/usb/gadget/udc/
- libs-$(CONFIG_SPL_DFU_SUPPORT) += drivers/usb/dwc3/
+ libs-$(CONFIG_SPL_USB_GADGET_SUPPORT) += drivers/usb/dwc3/
libs-y += dts/
libs-y += fs/
+libs-$(CONFIG_SPL_FPGA_SUPPORT) += drivers/fpga/
libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
libs-$(CONFIG_SPL_NET_SUPPORT) += net/
CONFIG_USB_XHCI_KEYSTONE
CONFIG_USB_XHCI_OMAP
CONFIG_USB_XHCI_PCI
-CONFIG_USB_XHCI_ZYNQMP
CONFIG_USER_LOWLEVEL_INIT
- CONFIG_USE_ARCH_MEMCPY
- CONFIG_USE_ARCH_MEMSET
CONFIG_USE_FDT
CONFIG_USE_INTERRUPT
CONFIG_USE_IRQ
addr = f.get('addr', None)
if not addr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = u_boot_utils.find_ram_base(u_boot_console) + (1024 * 1024 * 4)
+ timeout = f.get('timeout', u_boot_console.p.timeout)
+
fn = f['fn']
- output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+
expected_text = 'Bytes transferred = '
sz = f.get('size', None)
if sz:
projects / thirdparty / u-boot.git / commitdiff
