arm64: dts: qcom: ipq5424: Enable cpufreq

Add the qfprom, cpu clocks, A53 PLL and cpu-opp-table required for
CPU clock scaling.

Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
[ Added interconnect related entries, fix dt-bindings errors ]
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250811090954.2854440-5-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index bd891e39f33e18864a1d4c2bd8399b8b7486fec5..bbb539dbdf5c6827e228ac324f995108f9e7922b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -7,6 +7,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,apss-ipq.h>
 #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
 #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
 #include <dt-bindings/reset/qcom,ipq5424-gcc.h>
@@ -52,6 +53,11 @@
                        reg = <0x0>;
                        enable-method = "psci";
                        next-level-cache = <&l2_0>;
+                       clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
+                       clock-names = "cpu";
+                       operating-points-v2 = <&cpu_opp_table>;
+                       interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
+
                        l2_0: l2-cache {
                                compatible = "cache";
                                cache-level = <2>;
@@ -72,6 +78,10 @@
                        enable-method = "psci";
                        reg = <0x100>;
                        next-level-cache = <&l2_100>;
+                       clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
+                       clock-names = "cpu";
+                       operating-points-v2 = <&cpu_opp_table>;
+                       interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
 
                        l2_100: l2-cache {
                                compatible = "cache";
@@ -87,6 +97,10 @@
                        enable-method = "psci";
                        reg = <0x200>;
                        next-level-cache = <&l2_200>;
+                       clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
+                       clock-names = "cpu";
+                       operating-points-v2 = <&cpu_opp_table>;
+                       interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
 
                        l2_200: l2-cache {
                                compatible = "cache";
@@ -102,6 +116,10 @@
                        enable-method = "psci";
                        reg = <0x300>;
                        next-level-cache = <&l2_300>;
+                       clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
+                       clock-names = "cpu";
+                       operating-points-v2 = <&cpu_opp_table>;
+                       interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
 
                        l2_300: l2-cache {
                                compatible = "cache";
@@ -119,6 +137,36 @@
                };
        };
 
+       cpu_opp_table: opp-table-cpu {
+               compatible = "operating-points-v2-kryo-cpu";
+               opp-shared;
+               nvmem-cells = <&cpu_speed_bin>;
+
+               opp-816000000 {
+                       opp-hz = /bits/ 64 <816000000>;
+                       opp-microvolt = <850000>;
+                       opp-supported-hw = <0x3>;
+                       clock-latency-ns = <200000>;
+                       opp-peak-kBps = <816000>;
+               };
+
+               opp-1416000000 {
+                       opp-hz = /bits/ 64 <1416000000>;
+                       opp-microvolt = <850000>;
+                       opp-supported-hw = <0x3>;
+                       clock-latency-ns = <200000>;
+                       opp-peak-kBps = <984000>;
+               };
+
+               opp-1800000000 {
+                       opp-hz = /bits/ 64 <1800000000>;
+                       opp-microvolt = <1000000>;
+                       opp-supported-hw = <0x1>;
+                       clock-latency-ns = <200000>;
+                       opp-peak-kBps = <1272000>;
+               };
+       };
+
        memory@80000000 {
                device_type = "memory";
                /* We expect the bootloader to fill in the size */
@@ -388,6 +436,18 @@
                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               qfprom@a6000 {
+                       compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";
+                       reg = <0x0 0x000a6000 0x0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       cpu_speed_bin: cpu-speed-bin@234 {
+                               reg = <0x234 0x1>;
+                               bits = <0 8>;
+                       };
+               };
+
                tlmm: pinctrl@1000000 {
                        compatible = "qcom,ipq5424-tlmm";
                        reg = <0 0x01000000 0 0x300000>;
@@ -739,6 +799,15 @@
                        };
                };
 
+               apss_clk: clock-controller@fa80000 {
+                       compatible = "qcom,ipq5424-apss-clk";
+                       reg = <0x0 0x0fa80000 0x0 0x20000>;
+                       clocks = <&xo_board>,
+                                <&gcc GPLL0>;
+                       #clock-cells = <1>;
+                       #interconnect-cells = <1>;
+               };
+
                pcie3: pcie@40000000 {
                        compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
                        reg = <0x0 0x40000000 0x0 0xf1c>,