zynq: slcr: Wait 100ms till clk is properly setup

If you don't wait you will loose the first sent packet
even all bits in emacps are correctly setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index e5f710d4e25c8812927d067ee9fcf7121514d8d4..cfd66098620b6e832b52d696389a4962590649b5 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -166,7 +166,7 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
                /* Configure GEM_RCLK_CTRL */
                writel(rclk, &slcr_base->gem0_rclk_ctrl);
        }
-
+       udelay(100000);
 out:
        zynq_slcr_lock();
 }